hc_sl811.h

嵌入式USB HOST sl811hs的驱动程序

/*
 * SL811HS HCD (Host Controller Driver) for USB.
 * 
 * COPYRIGHT (C) by CYPRESS SEMICONDUCTOR INC 
 *
 */

#define URB_DEL 1

#define PORT_STAT_DEFAULT		0x0100
#define PORT_CONNECT_STAT  		0x1
#define PORT_ENABLE_STAT		0x2
#define PORT_SUSPEND_STAT		0x4
#define PORT_OVER_CURRENT_STAT		0x8
#define PORT_RESET_STAT			0x10
#define PORT_POWER_STAT			0x100
#define PORT_LOW_SPEED_DEV_ATTACH_STAT	0x200

#define PORT_CHANGE_DEFAULT		0x0
#define PORT_CONNECT_CHANGE		0x1
#define PORT_ENABLE_CHANGE		0x2
#define PORT_SUSPEND_CHANGE		0x4
#define PORT_OVER_CURRENT_CHANGE	0x8
#define PORT_RESET_CHANGE		0x10

/* Port Status Request info */

typedef struct portstat {
	__u16 portChange;
	__u16 portStatus;
} portstat_t;

typedef struct hcipriv {
	int irq;
	int disabled;		/* e.g. got a UE, we're hung */
	atomic_t resume_count;	/* defending against multiple resumes */
	struct ohci_regs *regs;	/* OHCI controller's memory */
	int hcport;		/* I/O base address */
	int hcport2;		/* I/O data reg addr */

	struct portstat *RHportStatus;	/* root hub port status */

	int intrstatus;
	__u32 hc_control;	/* copy of the hc control reg */

	int frame;

	__u8 *tl;
	int xferPktLen;
	int atl_len;
	int atl_buffer_len;
	int itl0_len;
	int itl1_len;
	int itl_buffer_len;
	int itl_index;
	int tl_last;
	int units_left;

} hcipriv_t;
struct hci;

#define PID_SETUP	0x2d	// USB Specification 1.1 Standard Definition
#define PID_SOF		0xA5
#define PID_IN		0x69
#define PID_OUT		0xe1

#define SL11H_HOSTCTLREG	0
#define SL11H_BUFADDRREG	1
#define SL11H_BUFLNTHREG	2
#define SL11H_PKTSTATREG	3	/* read */
#define SL11H_PIDEPREG		3	/* write */
#define SL11H_XFERCNTREG	4	/* read */
#define SL11H_DEVADDRREG	4	/* write */
#define SL11H_CTLREG1		5
#define SL11H_INTENBLREG	6
#define SL11H_HOSTCTLREG_B	8

#define SL11H_INTSTATREG	0x0D	/* write clears bitwise */
#define SL11H_HWREVREG		0x0E	/* read */
#define SL11H_SOFLOWREG		0x0E	/* write */
#define SL11H_SOFTMRREG		0x0F	/* read */
#define SL11H_CTLREG2		0x0F	/* write */
#define SL11H_DATA_START	0x10

/* Host control register bits (addr 0) */
#define SL11H_HCTLMASK_ARM	1
#define SL11H_HCTLMASK_ENBLEP	2
#define SL11H_HCTLMASK_WRITE	4
#define SL11H_HCTLMASK_ISOCH	0x10
#define SL11H_HCTLMASK_AFTERSOF	0x20
#define SL11H_HCTLMASK_SEQ	0x40
#define SL11H_HCTLMASK_PREAMBLE	0x80

/* Packet status register bits (addr 3) */
#define SL11H_STATMASK_ACK	1
#define SL11H_STATMASK_ERROR	2
#define SL11H_STATMASK_TMOUT	4
#define SL11H_STATMASK_SEQ	8
#define SL11H_STATMASK_SETUP	0x10
#define SL11H_STATMASK_OVF	0x20
#define SL11H_STATMASK_NAK	0x40
#define SL11H_STATMASK_STALL	0x80

/* Control register 1 bits (addr 5) */
#define SL11H_CTL1MASK_DSBLSOF	1
#define SL11H_CTL1MASK_NOTXEOF2	4
#define SL11H_CTL1MASK_DSTATE	0x18
#define SL11H_CTL1MASK_NSPD	0x20
#define SL11H_CTL1MASK_SUSPEND	0x40
#define SL11H_CTL1MASK_CLK12	0x80

#define SL11H_CTL1VAL_RESET	8

/* Interrut enable (addr 6) and interrupt status register bits (addr 0xD) */
#define SL11H_INTMASK_XFERDONE	1
#define SL11H_INTMASK_SOFINTR	0x10
#define SL11H_INTMASK_INSRMV	0x20
#define SL11H_INTMASK_USBRESET	0x40
#define SL11H_INTMASK_DSTATE	0x80	/* only in status reg */

/* HW rev and SOF lo register bits (addr 0xE) */
#define SL11H_HWRMASK_HWREV	0xF0

/* SOF counter and control reg 2 (addr 0xF) */
#define SL11H_CTL2MASK_SOFHI	0x3F
#define SL11H_CTL2MASK_DSWAP	0x40
#define SL11H_CTL2MASK_HOSTMODE	0xae