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<HTML><HEAD><TITLE>CSE 120 (Fall 2002) -- Homework #3</TITLE>
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<H2>CSE 120 (Fall 2002) -- Homework #3</H2><FONT color=blue size=+1><B>Out:
11/7</B></FONT><BR><FONT color=red size=+1><B>Due: 11/19</B></FONT>
<OL>
<P>
<LI><A
href="http://www.cse.ucsd.edu/classes/fa02/cse120/hw/vm-worksheet.html">Nachos
VM Worksheet</A>
<P></P>
<LI>Chapter 9: 9.10, 9.14
<P>9.10 Consider a paging system with the page table stored in memory.
<P> a. If a memory reference takes 200 nanoseconds, how long does
a paged memory reference take? <BR> b. If we add TLBs, and 75
percent of all page-table references are found in the TLBs, what is the
effective memory reference time? (Assume that finding a page-table entry in
the TLBs takes zero time, if the entry is there.)
<P>9.14 Explain why it is easier to share a reentrant module using
segmentation than it is to do so when pure paging is used.
<P></P>
<LI>Chapter 10: 10.2, 10.9, 10.19
<P>10.2 Assume that you have a page-reference string for a process with
<I>m</I> frames (initially all empty). The page-reference string has length
<I>p</I>; <I>n</I> distinct page numbers occur in it. Answer these questions
for any page-replacement algorithms:
<P> a. What is a lower bound on the number of page faults?
<BR> b. What is an upper bound on the number of page faults?
<P>10.9 Consider a demand-paging system with the following time-measured
utilizations:
<P> CPU utilization: 20% <BR> Paging disk: 97.7%
(demand, not storage)<BR> Other I/O devices: 5% <BR>
<P>For each of the following, say whether it will (or is likely to) improve
CPU utilization. Briefly explain your answers.
<P> a. Install a faster CPU <BR> b. Install a bigger
paging disk <BR> c. Increase the degree of multiprogramming
<BR> d. Decrease the degree of multiprogramming <BR>
e. Install more main memory <BR> f. Install a faster hard disk, or
multiple controllers with multiple hard disks <BR> g. Add
prepaging to the page-fetch algorithms <BR> h. Increase the page
size <BR>
<P>10.19 We have an operating system for a machine that uses base and
limit registers, but we have modified the machine to provide a page table. Can
we set up the page tables to simulate base and limit registers? How can we do
so, or why can we not do so?
<P></P>
<LI>[Crowley] Suppose we have an average of one page fault every 20,000,000
instructions, a normal instruction takes 2 nanoseconds, and a page fault
causes the instruction to take an additional 10 milliseconds. What is the
average instruction time, taking page faults into account? Redo the
calculation assuming that a normal instruction takes 1 nanoseconds instead of
2 nanoseconds.
<P></P>
<LI>[Crowley] Suppose we have a computer system with a 44-bit virtual address,
page size of 64K, and 4 bytes per page table entry.
<OL>
<LI>How many pages are in the virtual address space?
<LI>Suppose we use two-level paging and arrange for all page tables to fit
into a single page frame. How will the bits of the address be divided up?
<LI>Suppose we have a 4 GB program such that the entire program and all
necessary page tables (using two-level pages from above) are in memory.
(Note: It will be a <I>lot</I> of memory.) How much memory, in <B>page
frames</B>, is used by the program, including its page tables? </LI></OL>
<P></P>
<LI>[Tanenbaum] If FIFO page replacement is used with four page frames and
eight pages, how many page faults will occur with the reference string
0172327103 if the four frames are initially empty? Now repeat this problem for
LRU. </LI></OL><PRE>
</PRE>
<HR>
<ADDRESS><A href="mailto:voelker@cs.ucsd.edu">voelker@cs.ucsd.edu</A>
</ADDRESS></BODY></HTML>
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