hal_pxa250.h

linux下的usb开发

/************************************************************************
 * Philips ISP1362 hardware access layer driver for 
 * Intel PXA250 based Accelent IDP platform
 *
 * (c) 2002 Koninklijke Philips Electronics N.V., All rights reserved
 * 
 * This  source code and any compilation or derivative thereof is the
 * proprietary information of Koninklijke Philips Electronics N.V.
 * and is confidential in nature.
 * Under no circumstances is this software to be exposed to or placed
 * under an Open Source License of any type without the expressed
 * written permission of Koninklijke Philips Electronics N.V.
 *
 * File Name:	hal_pxa250.h
 *
 * History:	
 *
 *	Version	Date		Author		Comments
 * -------------------------------------------------
 * 	1.0		09/23/02	SYARRA		Initial Creation
 *
 * Note: use tab space 4
 ************************************************************************/

#ifndef __HAL_PXA250_H__
#define	__HAL_PXA250_H__

#define	 isp1362_command(reg,dev)	outw(reg,dev->io_cmd);udelay(1)
#define	 isp1362_read8(dev)		inb(dev->io_data)
#define	 isp1362_write8(data,dev)	outb(data,dev->io_data)
#define	 isp1362_read16(dev)		inw(dev->io_data)
#define	 isp1362_write16(data,dev)	outw(data,dev->io_data)

#define	 isp1362_printk			printk
#define	 isp1362_udelay			udelay
#define	 isp1362_mdelay			mdelay

#define	isp1362_vendor_id		0x04CC
#define	isp1362_product_id		0x1A64
#define	isp1362_product_string		{ 68,3, 			\
	'1',0, '3',0, '6',0, '2',0, '-',0, 'O',0, 'T',0, 'G',0, ' ',0,	\
	'M',0, 'A',0, 'S',0, 'S',0, ' ',0, 				\
	'S',0, 't',0, 'o',0, 'r',0, 'a',0, 'g',0, 'e',0, ' ',0,		\
	'P',0, 'X',0, 'A',0, '-',0, '2',0, '5',0, '0',0,		\
	' ',0, 'K',0, 'i',0, 't',0 }

	

typedef struct isp1362_hal {
	__u8	io_usage;	/* Number of drivers using IO */
	__u8	irq_usage;	/* NUmber of drivers using INT channel */
	void	*io_base;	/* IO port base */
	__u16	io_len;		/* IO port length */
	__u16	int_ch1;	/* Interrupt line 1 */
	__u16	int_ch2;	/* Interrupt line 2 */
	struct resource	resource;	/* IO resource, dummy one */
} isp1362_hal_t;

#define		DRIVER_VERSION				"v1.0"

/*
*  We have hardware support for asynchronous DMA transfers.  We can use PIO
*  mode as well.  The chips registers are mapped as follows:
*
*  Base address for pio mode: ioremap_nocache(PXA_CS2_BASE,PAGE_SIZE);
*  Physical addresses for DMA transfers: 
*  Note also that these are normally defined in the platform specific header
*  files.  DON'T define them within your driver, that's extremely non-portable.
*/  

#define ISP1362_DMA0_BASE	PXA_CS2_PHYS + 0x2000000
#define ISP1362_DMA1_BASE	PXA_CS2_PHYS + 0x1000000

#define ISP1362_IRQ_1		IRQ_GPIO(25)
#define ISP1362_IRQ_2		IRQ_GPIO(23)

#define ISP1362_IRQ_1_EDGE	GPIO_FALLING_EDGE
#define ISP1362_IRQ_2_EDGE	GPIO_FALLING_EDGE

#define DCMD_USBRX  	DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST16|DCMD_WIDTH2
#define	DCMD_USBTX 	DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST16|DCMD_WIDTH2 

#define DRCMRDREQ0	DRCMR0	// This is a register address, note...
#define DRCMRDREQ1	DRCMR1  // So is this

/* PXA IDP machine specific gunk: */
#define SET_D_SUSWKUP	(IDP_CPLD_GPIOL_VALUE |= 1)
#define CLR_D_SUSWKUP   (IDP_CPLD_GPIOL_VALUE &= ~0x1)
#define SET_H_SUSWKUP	(IDP_CPLD_GPIOL_VALUE |= 2)
#define CLR_H_SUSWKUP	(IDP_CPLD_GPIOL_VALUE &= ~0x2)

/* ISP1362 specific stuff here: */
/* Start with register commands */

#define CH_SETUP 0
#define CH_OUT   1
#define CH_IN    2

#endif /* __HAL_PXA250_H__ */