usb_phci.h

linux下的usb开发

#define 	PORT_POWER_SWITCHING			NO					/* Must be NO for Philips HC */
#define 	OVER_CURRENT_PROTECTION			YES
#define 	PER_PORT_OVER_CURRENT_REPORT	NO
#define 	POWER_ON_TO_POWER_GOOD_TIME		50UL				/* Max. = 512 Msec. Use even number */

/* Bit field definition for register HcRhDescriptorA */
#define 	HC_RH_DESCRIPTORA_NDP			0x000000FFUL		/* Number of downstream ports  */
#define 	HC_RH_DESCRIPTORA_PSM			0x00000100UL		/* Power Switching Mode        */
#define 	HC_RH_DESCRIPTORA_NPS			0x00000200UL		/* No Power Switching          */
#define 	HC_RH_DESCRIPTORA_OCPM			0x00000800UL		/* OverCurrent Protection Mode */
#define 	HC_RH_DESCRIPTORA_NOCP			0x00001000UL		/* No OverCurrent Protection   */
#define 	HC_RH_DESCRIPTORA_POTPGT		0xFF000000UL		/* Power On To Power Good Time */

/****************************/
/* HcRhDescriptorB Register */
/****************************/
#define 	DEVICE_REMOVABLE				0x00000000UL
#define 	PORT_POWER_MASK					0x00000000UL

/* Bit field definition for register HcRhDescriptorB */
#define 	HC_RH_DESCRIPTORB_PPCM			0xFFFF0000UL		/* Port Power Control Mask     */
#define 	HC_RH_DESCRIPTORB_DR			0x0000FFFFUL		/* Device Removable            */


/* Bit field definition for register HcRhStatus */
#define HC_RH_STATUS_LPS					0x00000001UL		/* R: Local Power Status       */


/*---------------------------------------------------*/
/* Index of the HC extended 16-bit registers */
/*---------------------------------------------------*/
#define 	REG_HW_MODE						0x20			/* Hardware configuration register */
#define 	REG_DMA_CNFG					0x21			/* DMA configuration register      */
#define 	REG_XFER_CNTR					0x22			/* Transfer counter register       */
#define 	REG_IRQ							0x24			/* Interrupt register              */
#define 	REG_IRQ_MASK					0x25			/* Interrupt enable register       */
#define 	REG_CHIP_ID						0x27			/* Chip ID register                */
#define 	REG_SCRATCH						0x28			/* Scratch register                */
#define 	REG_RESET_DEV					0xA9			/* Reset register                  */
#define 	REG_BUFF_STS					0x2C			/* Buffer status register          */


#define		REG_DIRECT_ADDR_LEN			0x32			/* Direct Addressing length+dir+addr */
#define		REG_DIRECT_ADDR_DATA		0x45			/* Direct Addressing data (port) */

#define		REG_ISTL_BUFF_LEN			0x30			/* ISTL buffer length register */
#define		REG_ISTL0_BUFF_PORT			0x40			/* ISTL0 buffer port register */
#define		REG_ISTL1_BUFF_PORT			0x42			/* ISTL1 buffer port register */
#define		REG_ISTL_TOGGLE_RATE		0x47			/* ISTL1 buffer toggle rate */

#define		REG_ATL_BUFF_LEN			0x34			/* ATL buffer length register */
#define		REG_ATL_BUFF_PORT			0x44			/* ATL buffer port register */
#define		REG_ATL_BLK_PL_SIZE			0x54			/* ATL buffer  payload block size */
#define		REG_ATL_THRESHOLD_COUNT		0x51			/* ATL buffer PTD done threshold counter register */
#define		REG_ATL_THRESHOLD_TIMEOUT	0x52			/* ATL buffer PTD done threshold timeout register */

#define		REG_ATL_PTD_DONE_MAP		0x1B			/* ATL Done map register (Read Only) */
#define		REG_ATL_PTD_SKIP_MAP		0x1C			/* ATL Skip map register */
#define		REG_ATL_PTD_LAST_PTD		0x1D			/* ATL buffer last PTD */
#define		REG_ATL_CURR_ACTIVE_PTD		0x1E			/* ATL buffer Current active PTD (Read Only) */


#define		REG_INTL_BUFF_LEN			0x33			/* INTL buffer length register */
#define		REG_INTL_BUFF_PORT			0x43			/* INTL buffer port register */
#define		REG_INTL_BLK_PL_SIZE		0x53			/* INTL buffer  payload block size */

#define		REG_INTL_PTD_DONE_MAP		0x17			/* INTL Done map register (Read Only) */
#define		REG_INTL_PTD_SKIP_MAP		0x18			/* INTL Skip map register */
#define		REG_INTL_PTD_LAST_PTD		0x19			/* INTL buffer last PTD */
#define		REG_INTL_CURR_ACTIVE_PTD	0x1A			/* INTL buffer Current active PTD (Read Only) */

#define 	PIC1_OCW1               	0x21
#define 	PIC1_CASCADE    			0xFB
#define 	PIC2_OCW1               	0xA1



/*------------------------------------------------------------------*/
/* Philips HC external Interrupts configuration						*/
/*------------------------------------------------------------------*/

/**********************************/
/* HardwareConfiguration Register */
/**********************************/
#define 	GLOBAL_INT_PIN_ENABLE      	YES
#define 	INT_EDGE_TRIGGERED         	NO
#define 	INT_ACTIVE_HIGH            	YES

/****************************/
/* InterruptEnable Register */
/****************************/
#define 	SOF_INT_ENABLED            	YES
#define 	ATL_INT_ENABLED            	NO
#define 	EOT_INT_ENABLED            	NO
#define 	OPR_INT_ENABLED            	YES
#define 	HC_SUSPEND_INT_ENABLED     	NO
#define 	HC_RESUME_INT_ENABLED      	NO

/****************************/
/* HcFmInterval Register    */
/****************************/
#define		FRAME_INTERVAL				0x00002EDFUL
#define		FS_LARGEST_DATA				(((FRAME_INTERVAL - 210) * 6) / 7)

/*-----------------------------------------------*/
/* Bit field definition for REG_HW_MODE register */
/*-----------------------------------------------*/
#define 	INT_PIN_ENABLE				0X0001			/* Bit 0    */
#define 	INT_PIN_TRIGGER				0X0002			/* Bit 1    */
#define 	INT_OUTPUT_POLARITY			0X0004			/* Bit 2    */
#define 	DATA_BUS_WIDTH				0X0018			/* Bit 4..3 */
#define		DREQ_OUT_POLARITY			0x0020			/* Bit 5	*/
#define		DACK_IN_POLARITY			0x0040			/* Bit 6	*/
#define		ONE_DMA					0x0080			/* Bit 7	*/
#define		DACK_MODE				0x0100			/* Bit 8	*/
#define		ONE_INT					0x0200			/* Bit 9	*/
#define		ANALOG_OC_ENABLE			0x0400			/* Bit 10 	*/
#define		SUSPEND_CLK_NOT_STOP			0x0800			/* Bit 11 	*/
#define		CONNECT_PLDN_15K_DS1			0x1000			/* Bit 12   */
#define		CONNECT_PLDN_15K_DS2			0x2000			/* Bit 13   */

#define		DATA_BUS_16BIT_WIDTH			0x0008

/*-----------------------------------------------*/
/* Bit field definition for REG_DMA_CNFG register */
/*-----------------------------------------------*/
#define 	DMA_WRITE_SELECT			0X0001			/* Bit 0    */
#define 	DMA_BUFF_TYPE				0X000E			/* Bit 1..3 */
#define 	DMA_ENABLE				0X0010			/* Bit 4   	*/
#define 	DMA_BURST_LENGTH			0X0060			/* Bit 5..6	*/
#define 	DMA_COUNTER_ENABLE			0X0080			/* Bit 7	*/

#define		DMA_BUFF_TYPE_ISTL0			0x0000			/* ISTL0	*/
#define		DMA_BUFF_TYPE_ISTL1			0x0002			/* ISTL1	*/
#define		DMA_BUFF_TYPE_INTL			0x0004			/* INTL		*/
#define		DMA_BUFF_TYPE_ATL			0x0006			/* ATL		*/
#define		DMA_BUFF_TYPE_DIR_ADDR			0x0008			/* DIR ADDR	*/

#define		DMA_1CYCLE_BURST_LEN			0x0000			/* Single Cycle 	*/
#define		DMA_4CYCLE_BURST_LEN			0x0020			/* 4 Cycle	burst	*/
#define		DMA_8CYCLE_BURST_LEN			0x0040			/* * Cycle burst 	*/

/*-------------------------------------------------------------*/
/* Bit field definition for REG_IRQ and REG_IRQ_MASK registers */
/*-------------------------------------------------------------*/
#define		SOF_INT					0X0001			/* Bit 0: SOF interrupts */
#define		ISTL_0_INT				0X0002			/* Bit 1: ISTL 0 interrupt */
#define		ISTL_1_INT				0X0004			/* Bit 2: ISTL 1 interrupt */
#define		EOT_INT					0X0008			/* Bit 3: End of transfer interrupt */
#define		OPR_INT					0X0010			/* Bit 4: HCOR int. */
#define		HC_SUSPEND_INT				0X0020			/* Bit 5 */
#define		HC_RESUME_INT				0X0040			/* Bit 6 */
#define		INTL_INT				0X0080			/* Bit 7: INTL interrupt */
#define		ATL_INT					0X0100			/* Bit 8: ALT interrupt */
#define		OTG_INT					0X0200			/* Bit 9: OTG interrupt */

/*-------------------------------------------------*/
/* Bit field definition for REG_BUFF_STS registers */
/*-------------------------------------------------*/
#define		ISTL_0_BUFF_FULL			0X0001			/* Bit 0: ISOA buffer full */
#define		ISTL_1_BUFF_FULL			0X0002			/* Bit 1: ISOB buffer full */
#define		INTL_ACTIVE				0X0004			/* Bit 2: INTL buffer full */
#define		ATL_ACTIVE				0X0008			/* Bit 3: ATL buffer full */
#define		RESET_PING_PONG				0x0010			/* Bit 4: Reset H/W ping Pong bit (bit10) */
#define		ISTL_0_ACTIVE_STATUS			0X0020			/* Bit 5: ISOA buffer done */
#define		ISTL_1_ACTIVE_STATUS			0X0040			/* Bit 6: ISOB buffer done */
#define		ISTL_0_BUFF_DONE			0X0100			/* Bit 8: ISOA buffer done */
#define		ISTL_1_BUFF_DONE			0X0200			/* Bit 9: ISOB buffer done */
#define		ACTIVE_PING_PONG_PAIR			0X0400			/* Bit 10: ATL ping-pong active */

/*-----------------------------------------------------------*/
/* Definitions related to Philips Transfer Descriptors (PTD) */
/*-----------------------------------------------------------*/

/* Bit field definition for PTD byte 0 */
#define 	PTD_ACTUAL_BYTES70  			0XFF			/* Bit 7..0 */

/* Bit field definition for PTD byte 1 */
#define 	PTD_COMPLETION_CODE 			0XF0			/* Bit 7..4 */
#define 	PTD_ACTIVE      			0X08			/* Bit 3 */
#define 	PTD_TOGGLE      			0X04			/* Bit 2 */
#define 	PTD_ACTUAL_BYTES98  			0X03			/* Bit 1..0 */

/* Bit field definition for PTD byte 2 */
#define 	PTD_MAXPACKET70 			0XFF			/* Bit 7..0 */

/* Bit field definition for PTD byte 3 */
#define 	PTD_ED          			0XF0			/* Bit 7..4 */
#define 	PTD_LAST        			0X08			/* Bit 3 */
#define 	PTD_SPEED       			0X04			/* Bit 2 */
#define 	PTD_MAXPACKET98 			0X03 			/* Bit 1..0 */

/* Bit field definition for PTD byte 4 */
#define 	PTD_TOTAL70     			0XFF			/* Bit 7..0 */

/* Bit field definition for PTD byte 5 */
#define 	PTD_DIR         			0X0C			/* Bit 3..2 */
#define 	PTD_TOTAL98     			0X03			/* Bit 1..0 */

/* Bit field definition for PTD byte 6 */
#define 	PTD_FORMAT      			0X80			/* Bit 7 */
#define 	PTD_FUNCTION    			0X7F			/* Bit 6..0 */

#define		HC_PTD_HEADER_SIZE			8
#define		HC_RAM_SIZE					4096		/* (ATL + INTL + 2*ISTL < 4096) */
#define		HC_ATL_BUFFER_LENGTH		1536
#define		HC_ATL_BLK_PL_SIZE			256 
#define		HC_ISTL_BUFFER_LENGTH		1024
#define		HC_ISTL_BLK_PL_SIZE			128

#define		HC_INTL_BUFFER_LENGTH		512
#define		HC_INTL_BLK_PL_SIZE			64

#define		HC_ISTL_DEF_TOGGLE_RATE		5			/* based on num of isoc pipes supported and max pl size we can change this number */
#define		HC_ISTL_0_ADDRESS			0
#define		HC_ISTL_1_ADDRESS			(HC_ISTL_0_ADDRESS + HC_ISTL_BUFFER_LENGTH)
#define		HC_INTL_ADDRESS				(HC_ISTL_1_ADDRESS + HC_ISTL_BUFFER_LENGTH)
#define		HC_ATL_ADDRESS				(HC_INTL_ADDRESS+HC_INTL_BUFFER_LENGTH)

#define		HC_DIR_ADDR_INCREMENT		0x00000000
#define		HC_DIR_ADDR_DECREMENT		0x00008000

#define		HC_DEF_ATL_THRESHOLD_COUNT	1		/* 1 interrupt per 1 ptd done */
#define		HC_DEF_ATL_THRESHOLD_TIMEOUT	5	/* timeout after 5 milli second */

#define		HC_ATL_BLK_SIZE				(HC_ATL_BLK_PL_SIZE+HC_PTD_HEADER_SIZE)
#define		HC_INTL_BLK_SIZE			(HC_INTL_BLK_PL_SIZE+HC_PTD_HEADER_SIZE)
#define		HC_ISTL_BLK_SIZE			(HC_ISTL_BLK_PL_SIZE+HC_PTD_HEADER_SIZE)

#define		TD_PTD_MAX_ATL_TDS			(HC_ATL_BUFFER_LENGTH/HC_ATL_BLK_SIZE)
#define		TD_PTD_MAX_INTL_TDS			(HC_INTL_BUFFER_LENGTH/HC_INTL_BLK_SIZE)
#define		TD_PTD_MAX_ISTL_TDS			(HC_ISTL_BUFFER_LENGTH/HC_ISTL_BLK_SIZE)

/* assuming ISTL buffer size is greater than HC_ATL_BLK_PL_SIZE  (or) use
 * max_hcd(HC_ATL_BLK_PL_SIZE, max_hcd(HC_INTL_BLK_PL_SIZE,HC_ISTL_BUFFER_LENGTH))
 */
#define		TD_PTD_MAX_BUFF_SIZE		HC_ISTL_BUFFER_LENGTH

#define		TD_PTD_MAX_BUFF_TDS			32		/* Maximum atl & ITl td's served by PHC
													are 32 only, assuming istl does not go more
													than 32 ptd's */

#define		TD_PTD_INV_PTD_INDEX		0xFF	/* Invalid td-ptd index */

#define		TD_PTD_PING					0x80			/* Ping PTD */
#define		TD_PTD_PONG					0xC0			/* Pong PTD */
#define		TD_PTD_NO_PING_PONG			0x00			/* ordinary ptd */

#define		TD_PTD_PING_FILLED			0x01	/* PING PTD FILLED IN RAM BUFFER */
#define		TD_PTD_PONG_FILLED			0x02	/* PING PTD FILLED IN RAM BUFFER */

/* td ptd status */
#define		TD_PTD_NEW					0	/* PTD is not active */
#define		TD_PTD_OPER					1	/* PTD is active */
#define		TD_PTD_SKIP					2	/* PTD is to be skipped */
#define		TD_PTD_DEL					3	/* PTD is to be removed */

typedef struct td_ptd_map {
__u8		state;			/* ACTIVE, SKIP, NOT_ACTIVE, TO_BE_REMOVED */
//__u8		ptd_cnt;		/* Number of ISOC ptds in the ram buffer in the starting td-ptd map only  */
__u8		ping_pong;		/* ping pong filling status (PING or PONG or NO_PING_PONG */
__u16		total_bytes;	/* Total Number of bytes for this PTD (including header) */
__u32		ptd_bitmap;		/* Bitmap of this ptd in HC */
__u32		ram_addr;		/* ram_addr of this ptd */
ed_t		*ed;			/* ed pointer */
td_t		*td;			/* td pointer */
} td_ptd_map_t;

/* buffer type for Philips HC */
#define		TD_PTD_BUFF_TYPE_ATL		0	/* ATL buffer */
#define		TD_PTD_BUFF_TYPE_INTL		1	/* INTL buffer */
#define		TD_PTD_BUFF_TYPE_ISTL0		2	/* ISTL2 buffer */
#define		TD_PTD_BUFF_TYPE_ISTL1		3	/* ISTL1 buffer */

#define		TD_PTD_TOTAL_BUFF_TYPES			(TD_PTD_BUFF_TYPE_ISTL1+1)



typedef struct hc_ram_buff_regs {
	__u16				buffer_length;			/* Buffer length of RAM buffer */
	__u16				buffer_port;			/* RAM buffer port number (for accessing) */
	__u16				block_pl_size;			/* block payload size (for INTL & ATL only ) */
	__u16				toggle_rate;			/* ISOC buffer toggle rate (ISTL only) */
	__u32				last_ptd;				/* Last ptd in the hc RAM buffer */
	__u32				ptd_done_map;			/* Done ptd map in the hc RAM buffer */
	__u32				ptd_skip_map;			/* skip ptd map in the hc RAM buffer */
	__u32				curr_active_ptd;		/* Current active ptd in hc RAM buffer */
	__u8				threshold_count;		/* Thereshold ptd count for ATL buffer */
	__u8				threshold_timeout;		/* Thereshold timeout units for ATL buffer */
} hc_ram_buff_regs_t;

typedef struct td_ptd_map_buff {
	__u8				buffer_type;			/* Buffer type: BUFF_TYPE_ATL/INTL/ISTL0/ISTL1 */
	__u8				ping_pong_status;		/* Ping_Pong mechanism is being used or not */		
	__u8				ping_ptd_index;			/* index of the ping PTD */
	__u8				pong_ptd_index;			/* index of the pong PTD */
	__u8				active_ptds;			/* number of active td's in the buffer */
	__u8				total_ptds;				/* Total number of td's present in the buffer (active + tobe removed + skip) */
	__u8				max_ptds;				/* Maximum number of ptd's this buffer can withstand */
	__u32				active_ptd_bitmap;		/* Active PTD's bitmap */
	__u32				skip_ptd_bitmap;		/* skip PTD's bitmap */
	__u32				pending_ptd_bitmap;		/* skip PTD's bitmap */
	__u32				active_ptd_bitmask;		/* active ptd bitmask */
	__u16				ram_buff_addr;			/* Ram Buffer Address */	
	__u32				frame_number;			/* Isoc frame Number */
	td_t				*done_head;				/* Done td's head pointer */
	hc_ram_buff_regs_t	regs;					/* HC ram buffer registers (copy of hc registers maintained at HCD */
	td_ptd_map_t		map_list[TD_PTD_MAX_BUFF_TDS];	/* td_ptd_map list */
} td_ptd_map_buff_t;


#define		PTD_CC_MASK					0xF0			/* PTD completion code mask */
#define		ATL_PTD_HEADER_BYTE7		0x00			/* Atl buffer ptd header 7th byte */
#define		RAM_BUFF_ALIGNMENT			0x4

#define		ALIGN_RAM_BUFF_LENGTH(x)	while( (x) & (RAM_BUFF_ALIGNMENT-1)) {(x)++;}


#define		PHCI_DRIVER_VERSION			"v1.0"
#define		HC_NUMBER					"1362"

#define		MAX_BULK_TD_BUFF_SIZE		HC_ATL_BLK_PL_SIZE
#define		MAX_CNTL_TD_BUFF_SIZE		HC_ATL_BLK_PL_SIZE

#ifdef CONFIG_USB_HCDC_OTG
extern 	void	phci_otg_port_control(void *priv, __u8	cmd, __u32 *data);
extern	int	phci_register_otg(phci_otg_data_t	*otg_data);
extern	void	phci_unregister_otg(phci_otg_data_t	*otg_data);
extern	void	phci_otg_port_control(void *priv, __u8	cmd, __u32 *data);
#endif /* CONFIG_USB_HCDC_OTG */

#endif	/* __USB_PHCI_H__ */