📄 bahe.mfr
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Frequency Analysis Report:
-------------------------
Design Name: BAHE
Part Name: ispLSI1016E-80LJ44
This report contains the maximum frequency at which the design
can be operated. It also lists the path that determines the
maximum frequency and the number of GLB levels.
The remaining internal register paths and their frequencies
are also listed, if the source and the registers are driven
by the same reference clock.
Maximum Operating Frequency: 27 MHz
The clock period is 36.90.
Clock period = path delay + clock-to-output delay + setup time
path delay: 34.50
clock-to-output delay: 1.60
setup time: 0.80
The following path determines the frequency:
Startpoint: GLB_L8_PIN/Q0
(edge-triggered flip-flop)
Endpoint: GLB_L2_PIN/D0
(edge-triggered flip-flop)
No. of GLB Levels: 3
Internal Register Paths and Frequencies:
Source Source Destination Destination Clock Frequency # of GLB
Reference Register Reference Register Period [MHz] Levels
Clock Name Clock Name [ns]
==----------------------------------------------------------------------------------------------------------------
RIGHT GLB_L8_PIN/Q0 RIGHT GLB_L2_PIN/D0 36.90 27 3
LEFT GLB_L8_PIN/Q0 LEFT GLB_L0_PIN/D0 24.30 41 2
LEFT GLB_L0_PIN/Q0 LEFT GLB_L0_PIN/D0 13.00 77 1
LEFT GLB_W/Q0 LEFT GLB_L0_PIN/D0 12.90 78 1
LEFT GLB_L1_PIN/Q0 LEFT GLB_L0_PIN/D0 12.90 78 1
LEFT GLB_L8_PIN/Q0 LEFT GLB_L1_PIN/D0 36.90 27 3
LEFT GLB_L0_PIN/Q0 LEFT GLB_L1_PIN/D0 25.10 40 2
LEFT GLB_L2_PIN/Q0 LEFT GLB_L1_PIN/D0 24.70 40 2
LEFT GLB_W/Q0 LEFT GLB_L1_PIN/D0 24.50 41 2
LEFT GLB_L1_PIN/Q0 LEFT GLB_L1_PIN/D0 12.90 78 1
LEFT GLB_L8_PIN/Q0 LEFT GLB_L2_PIN/D0 36.90 27 3
LEFT GLB_L0_PIN/Q0 LEFT GLB_L2_PIN/D0 25.10 40 2
LEFT GLB_W/Q0 LEFT GLB_L2_PIN/D0 24.50 41 2
LEFT GLB_L1_PIN/Q0 LEFT GLB_L2_PIN/D0 12.90 78 1
LEFT GLB_L3_PIN/Q0 LEFT GLB_L2_PIN/D0 12.60 79 1
LEFT GLB_L2_PIN/Q0 LEFT GLB_L2_PIN/D0 12.40 81 1
LEFT GLB_L8_PIN/Q0 LEFT GLB_L3_PIN/D0 36.90 27 3
LEFT GLB_L0_PIN/Q0 LEFT GLB_L3_PIN/D0 25.10 40 2
LEFT GLB_L2_PIN/Q0 LEFT GLB_L3_PIN/D0 24.70 40 2
LEFT GLB_W/Q0 LEFT GLB_L3_PIN/D0 24.50 41 2
LEFT GLB_L4_PIN/Q0 LEFT GLB_L3_PIN/D0 12.60 79 1
LEFT GLB_L3_PIN/Q0 LEFT GLB_L3_PIN/D0 12.40 81 1
LEFT GLB_L8_PIN/Q0 LEFT GLB_L4_PIN/D0 24.80 40 2
LEFT GLB_L0_PIN/Q0 LEFT GLB_L4_PIN/D0 13.00 77 1
LEFT GLB_W/Q0 LEFT GLB_L4_PIN/D0 12.90 78 1
LEFT GLB_L5_PIN/Q0 LEFT GLB_L4_PIN/D0 12.80 78 1
LEFT GLB_L3_PIN/Q0 LEFT GLB_L4_PIN/D0 12.60 79 1
LEFT GLB_L4_PIN/Q0 LEFT GLB_L4_PIN/D0 12.40 81 1
LEFT GLB_L8_PIN/Q0 LEFT GLB_W/D0 24.80 40 2
LEFT GLB_L0_PIN/Q0 LEFT GLB_W/D0 13.00 77 1
LEFT GLB_W/Q0 LEFT GLB_W/D0 12.40 81 1
LEFT GLB_L8_PIN/Q0 LEFT GLB_L5_PIN/D0 36.90 27 3
LEFT GLB_L0_PIN/Q0 LEFT GLB_L5_PIN/D0 25.10 40 2
LEFT GLB_W/Q0 LEFT GLB_L5_PIN/D0 24.50 41 2
LEFT GLB_L6_PIN/Q0 LEFT GLB_L5_PIN/D0 12.80 78 1
LEFT GLB_L4_PIN/Q0 LEFT GLB_L5_PIN/D0 12.60 79 1
LEFT GLB_L5_PIN/Q0 LEFT GLB_L5_PIN/D0 12.40 81 1
LEFT GLB_L8_PIN/Q0 LEFT GLB_L6_PIN/D0 36.90 27 3
LEFT GLB_L0_PIN/Q0 LEFT GLB_L6_PIN/D0 25.10 40 2
LEFT GLB_W/Q0 LEFT GLB_L6_PIN/D0 24.50 41 2
LEFT GLB_L6_PIN/Q0 LEFT GLB_L6_PIN/D0 12.80 78 1
LEFT GLB_L7_PIN/Q0 LEFT GLB_L6_PIN/D0 12.80 78 1
LEFT GLB_L5_PIN/Q0 LEFT GLB_L6_PIN/D0 12.80 78 1
LEFT GLB_L8_PIN/Q0 LEFT GLB_L7_PIN/D0 36.90 27 3
LEFT GLB_L0_PIN/Q0 LEFT GLB_L7_PIN/D0 25.10 40 2
LEFT GLB_W/Q0 LEFT GLB_L7_PIN/D0 24.50 41 2
LEFT GLB_L7_PIN/Q0 LEFT GLB_L7_PIN/D0 12.80 78 1
LEFT GLB_L6_PIN/Q0 LEFT GLB_L7_PIN/D0 12.80 78 1
LEFT GLB_L8_PIN/Q0 LEFT GLB_L8_PIN/D0 24.30 41 2
LEFT GLB_L0_PIN/Q0 LEFT GLB_L8_PIN/D0 13.00 77 1
LEFT GLB_W/Q0 LEFT GLB_L8_PIN/D0 12.90 78 1
LEFT GLB_L7_PIN/Q0 LEFT GLB_L8_PIN/D0 12.80 78 1
==-------------------------------------------------------------------------------------------
Information for flip-flop:
Global reset-to-output delay: 7.10
Clock-to-output delay: 1.60
User reset-to-output delay: 7.10
Data-to-output delay: 0.00
Setup time: 0.80
Hold time: 3.00
Pulse-width time: 5.00
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