bahe.sim

电子拔河游戏的实现, 二极管,移位寄存器和计数器的实现

      PIN  A0  IN  B6_F0;
   END;  // SYM PGORG1

   SYM PGORF73 GLB_B6_F0 GLB glb00;
      PIN  Z0  OUT  B6_F0;
      PIN  A2  IN  B6_P1;
      PIN  A1  IN  B6_P2;
      PIN  A0  IN  B6_P3;
   END;  // SYM PGORF43

   SYM PGBUFI GLB_B6_CLK GLB glb00;
      PIN  Z0  OUT  B6_CLK;
      PIN  A0  IN  W_C_clk2;
   END;  // SYM PGBUFK

   SYM PGBUFI GLB_W_D0 GLB glb00;
      PIN  Z0  OUT  W_D0;
      PIN  A0  IN  B6_X1O;
   END;  // SYM PGBUFD

   SYM PGBUFI GLB_W_D GLB glb00;
      PIN  Z0  OUT  W_D;
      PIN  A0  IN  B6_X0O;
   END;  // SYM PGBUFXO

   SYM PGBUFI GLB_B6_IN16 GLB glb00;
      PIN  Z0  OUT  B6_IN16;
      PIN  A0  IN  W_ffb;
   END;  // SYM PGBUFI

   SYM PGBUFI GLB_B6_IN12 GLB glb00;
      PIN  Z0  OUT  B6_IN12;
      PIN  A0  IN  _AND_704_grp;
   END;  // SYM PGBUFI

   SYM PGBUFI GLB_B6_IN15 GLB glb00;
      PIN  Z0  OUT  B6_IN15;
      PIN  A0  IN  L0_PIN_grp;
   END;  // SYM PGBUFI

   SYM PGBUFI GLB_B6_IN8 GLB glb00;
      PIN  Z0  OUT  B6_IN8;
      PIN  A0  IN  RIGHTX_grp;
   END;  // SYM PGBUFI

   SYM PGXOR2 GLB_B6_X1O GLB glb00;
      PIN  Z0  OUT  B6_X1O;
      PIN  A1  IN  GND;
      PIN  A0  IN  B6_G2;
   END;  // SYM PGXOR2

   SYM PGXOR2 GLB_B6_X0O GLB glb00;
      PIN  Z0  OUT  B6_X0O;
      PIN  A1  IN  GND;
      PIN  A0  IN  B6_G3;
   END;  // SYM PGXOR2

   SYM PGDFFR GLB_W GLB glb00;
      PIN  Q0  OUT  W;
      PIN  RNESET  IN  !RESET_glb;
      PIN  CD  IN  GND;
      PIN  CLK  IN  B6_CLK;
      PIN  D0  IN  W_D0;
   END;  // SYM PGDFFR

   SYM PGINVI GLB_B6_IN9B GLB glb00;
      PIN  ZN0  OUT  B6_IN9B;
      PIN  A0  IN  CLRX_grp;
   END;  // SYM PGINVI

   SYM PXIN IOC_RESET IOC XRESET;
      PIN  Z0  OUT  !RESET;
      PIN  XI0  IN  !XRESET;
   END;  // SYM PXINR

   SYM PXIN IOC_IO7_IBUFO IOC RIGHT;
      PIN  Z0  OUT  IO7_IBUFO;
      PIN  XI0  IN  RIGHT;
   END;  // SYM PXIN

   SYM PGBUFI IOC_RIGHTX IOC RIGHT;
      PIN  Z0  OUT  RIGHTX;
      PIN  A0  IN  IO7_IBUFO;
   END;  // SYM PXBUFI

   SYM PXIN IOC_IO30_IBUFO IOC LEFT;
      PIN  Z0  OUT  IO30_IBUFO;
      PIN  XI0  IN  LEFT;
   END;  // SYM PXIN

   SYM PGBUFI IOC_LEFTX IOC LEFT;
      PIN  Z0  OUT  LEFTX;
      PIN  A0  IN  IO30_IBUFO;
   END;  // SYM PXBUFI

   SYM PXIN IOC_IO6_IBUFO IOC CLR;
      PIN  Z0  OUT  IO6_IBUFO;
      PIN  XI0  IN  CLR;
   END;  // SYM PXIN

   SYM PGBUFI IOC_CLRX IOC CLR;
      PIN  Z0  OUT  CLRX;
      PIN  A0  IN  IO6_IBUFO;
   END;  // SYM PXBUFI

   SYM PXOUT IOC_L8 IOC L8;
      PIN  XO0  OUT  L8;
      PIN  A0  IN  IO1_OBUFI;
   END;  // SYM PXOUT

   SYM PGBUFI IOC_IO1_OBUFI IOC L8;
      PIN  Z0  OUT  IO1_OBUFI;
      PIN  A0  IN  L8_PIN_iomux;
   END;  // SYM PXBUFO

   SYM PXOUT IOC_L7 IOC L7;
      PIN  XO0  OUT  L7;
      PIN  A0  IN  IO8_OBUFI;
   END;  // SYM PXOUT

   SYM PGBUFI IOC_IO8_OBUFI IOC L7;
      PIN  Z0  OUT  IO8_OBUFI;
      PIN  A0  IN  L7_PIN_iomux;
   END;  // SYM PXBUFO

   SYM PXOUT IOC_L6 IOC L6;
      PIN  XO0  OUT  L6;
      PIN  A0  IN  IO2_OBUFI;
   END;  // SYM PXOUT

   SYM PGBUFI IOC_IO2_OBUFI IOC L6;
      PIN  Z0  OUT  IO2_OBUFI;
      PIN  A0  IN  L6_PIN_iomux;
   END;  // SYM PXBUFO

   SYM PXOUT IOC_L5 IOC L5;
      PIN  XO0  OUT  L5;
      PIN  A0  IN  IO13_OBUFI;
   END;  // SYM PXOUT

   SYM PGBUFI IOC_IO13_OBUFI IOC L5;
      PIN  Z0  OUT  IO13_OBUFI;
      PIN  A0  IN  L5_PIN_iomux;
   END;  // SYM PXBUFO

   SYM PXOUT IOC_L4 IOC L4;
      PIN  XO0  OUT  L4;
      PIN  A0  IN  IO22_OBUFI;
   END;  // SYM PXOUT

   SYM PGBUFI IOC_IO22_OBUFI IOC L4;
      PIN  Z0  OUT  IO22_OBUFI;
      PIN  A0  IN  L4_PIN_iomux;
   END;  // SYM PXBUFO

   SYM PXOUT IOC_L3 IOC L3;
      PIN  XO0  OUT  L3;
      PIN  A0  IN  IO14_OBUFI;
   END;  // SYM PXOUT

   SYM PGBUFI IOC_IO14_OBUFI IOC L3;
      PIN  Z0  OUT  IO14_OBUFI;
      PIN  A0  IN  L3_PIN_iomux;
   END;  // SYM PXBUFO

   SYM PXOUT IOC_L2 IOC L2;
      PIN  XO0  OUT  L2;
      PIN  A0  IN  IO31_OBUFI;
   END;  // SYM PXOUT

   SYM PGBUFI IOC_IO31_OBUFI IOC L2;
      PIN  Z0  OUT  IO31_OBUFI;
      PIN  A0  IN  L2_PIN_iomux;
   END;  // SYM PXBUFO

   SYM PXOUT IOC_L1 IOC L1;
      PIN  XO0  OUT  L1;
      PIN  A0  IN  IO15_OBUFI;
   END;  // SYM PXOUT

   SYM PGBUFI IOC_IO15_OBUFI IOC L1;
      PIN  Z0  OUT  IO15_OBUFI;
      PIN  A0  IN  L1_PIN_iomux;
   END;  // SYM PXBUFO

   SYM PXOUT IOC_L0 IOC L0;
      PIN  XO0  OUT  L0;
      PIN  A0  IN  IO11_OBUFI;
   END;  // SYM PXOUT

   SYM PGBUFI IOC_IO11_OBUFI IOC L0;
      PIN  Z0  OUT  IO11_OBUFI;
      PIN  A0  IN  L0_PIN_iomux;
   END;  // SYM PXBUFO

   SYM PGBUFI GRP_L2_PIN_buff1_grpi  GRP;
      PIN  Z0  OUT  L2_PIN_buff1_grpi;
      PIN  A0  IN  L2_PIN_buff1;
   END;  // SYM PRBUFOB

   SYM PGBUFI GRP_L2_PIN_buff1_grp  GRP;
      PIN  Z0  OUT  L2_PIN_buff1_grp;
      PIN  A0  IN  L2_PIN_buff1_grpi;
   END;  // SYM PRBUFO1

   SYM PGBUFI GRP_L2_PIN_grpi  GRP;
      PIN  Z0  OUT  L2_PIN_grpi;
      PIN  A0  IN  L2_PIN;
   END;  // SYM PRBUFOB

   SYM PGBUFI GRP_L2_PIN_grp  GRP;
      PIN  Z0  OUT  L2_PIN_grp;
      PIN  A0  IN  L2_PIN_grpi;
   END;  // SYM PRBUFO1

   SYM PGBUFI GRP_L2_PIN_ffb  GRP;
      PIN  Z0  OUT  L2_PIN_ffb;
      PIN  A0  IN  L2_PIN;
   END;  // SYM PGBUFF

   SYM PGBUFI GRP_L2_PIN_iomux  GRP;
      PIN  Z0  OUT  L2_PIN_iomux;
      PIN  A0  IN  L2_PIN;
   END;  // SYM PRBUFX1

   SYM PGBUFI GRP_L7_PIN_grpi  GRP;
      PIN  Z0  OUT  L7_PIN_grpi;
      PIN  A0  IN  L7_PIN;
   END;  // SYM PRBUFOB

   SYM PGBUFI GRP_L7_PIN_grp  GRP;
      PIN  Z0  OUT  L7_PIN_grp;
      PIN  A0  IN  L7_PIN_grpi;
   END;  // SYM PRBUFO2

   SYM PGBUFI GRP_L7_PIN_iomux  GRP;
      PIN  Z0  OUT  L7_PIN_iomux;
      PIN  A0  IN  L7_PIN;
   END;  // SYM PRBUFX1

   SYM PGBUFI GRP_L5_PIN_ffb  GRP;
      PIN  Z0  OUT  L5_PIN_ffb;
      PIN  A0  IN  L5_PIN;
   END;  // SYM PGBUFF

   SYM PGBUFI GRP_L5_PIN_grpi  GRP;
      PIN  Z0  OUT  L5_PIN_grpi;
      PIN  A0  IN  L5_PIN;
   END;  // SYM PRBUFOB

   SYM PGBUFI GRP_L5_PIN_grp  GRP;
      PIN  Z0  OUT  L5_PIN_grp;
      PIN  A0  IN  L5_PIN_grpi;
   END;  // SYM PRBUFO2

   SYM PGBUFI GRP_L5_PIN_iomux  GRP;
      PIN  Z0  OUT  L5_PIN_iomux;
      PIN  A0  IN  L5_PIN;
   END;  // SYM PRBUFX1

   SYM PGBUFI GRP_L3_PIN_ffb  GRP;
      PIN  Z0  OUT  L3_PIN_ffb;
      PIN  A0  IN  L3_PIN;
   END;  // SYM PGBUFF

   SYM PGBUFI GRP_L3_PIN_grpi  GRP;
      PIN  Z0  OUT  L3_PIN_grpi;
      PIN  A0  IN  L3_PIN;
   END;  // SYM PRBUFOB

   SYM PGBUFI GRP_L3_PIN_grp  GRP;
      PIN  Z0  OUT  L3_PIN_grp;
      PIN  A0  IN  L3_PIN_grpi;
   END;  // SYM PRBUFO1

   SYM PGBUFI GRP_L3_PIN_iomux  GRP;
      PIN  Z0  OUT  L3_PIN_iomux;
      PIN  A0  IN  L3_PIN;
   END;  // SYM PRBUFX1

   SYM PGBUFI GRP_L1_PIN_grpi  GRP;
      PIN  Z0  OUT  L1_PIN_grpi;
      PIN  A0  IN  L1_PIN;
   END;  // SYM PRBUFOB

   SYM PGBUFI GRP_L1_PIN_grp  GRP;
      PIN  Z0  OUT  L1_PIN_grp;
      PIN  A0  IN  L1_PIN_grpi;
   END;  // SYM PRBUFO3

   SYM PGBUFI GRP_L1_PIN_iomux  GRP;
      PIN  Z0  OUT  L1_PIN_iomux;
      PIN  A0  IN  L1_PIN;
   END;  // SYM PRBUFX1

   SYM PGBUFI GRP_CLRX_grp  GRP;
      PIN  Z0  OUT  CLRX_grp;
      PIN  A0  IN  CLRX;
   END;  // SYM PRBUFO4

   SYM PGBUFI GRP_L0_PIN_grpi  GRP;
      PIN  Z0  OUT  L0_PIN_grpi;
      PIN  A0  IN  L0_PIN;
   END;  // SYM PRBUFOB

   SYM PGBUFI GRP_L0_PIN_grp  GRP;
      PIN  Z0  OUT  L0_PIN_grp;
      PIN  A0  IN  L0_PIN_grpi;
   END;  // SYM PRBUFO4

   SYM PGBUFI GRP_L0_PIN_iomux  GRP;
      PIN  Z0  OUT  L0_PIN_iomux;
      PIN  A0  IN  L0_PIN;
   END;  // SYM PRBUFX1

   SYM PGBUFI GRP_L4_PIN_grpi  GRP;
      PIN  Z0  OUT  L4_PIN_grpi;
      PIN  A0  IN  L4_PIN;
   END;  // SYM PRBUFOB

   SYM PGBUFI GRP_L4_PIN_grp  GRP;
      PIN  Z0  OUT  L4_PIN_grp;
      PIN  A0  IN  L4_PIN_grpi;
   END;  // SYM PRBUFO1

   SYM PGBUFI GRP_L4_PIN_ffb  GRP;
      PIN  Z0  OUT  L4_PIN_ffb;
      PIN  A0  IN  L4_PIN;
   END;  // SYM PGBUFF

   SYM PGBUFI GRP_L4_PIN_iomux  GRP;
      PIN  Z0  OUT  L4_PIN_iomux;
      PIN  A0  IN  L4_PIN;
   END;  // SYM PRBUFX1

   SYM PGBUFI GRP_L6_PIN_grpi  GRP;
      PIN  Z0  OUT  L6_PIN_grpi;
      PIN  A0  IN  L6_PIN;
   END;  // SYM PRBUFOB

   SYM PGBUFI GRP_L6_PIN_grp  GRP;
      PIN  Z0  OUT  L6_PIN_grp;
      PIN  A0  IN  L6_PIN_grpi;
   END;  // SYM PRBUFO2

   SYM PGBUFI GRP_L6_PIN_iomux  GRP;
      PIN  Z0  OUT  L6_PIN_iomux;
      PIN  A0  IN  L6_PIN;
   END;  // SYM PRBUFX1

   SYM PGBUFI GRP_L8_PIN_ffb  GRP;
      PIN  Z0  OUT  L8_PIN_ffb;
      PIN  A0  IN  L8_PIN;
   END;  // SYM PGBUFF

   SYM PGBUFI GRP_L8_PIN_grpi  GRP;
      PIN  Z0  OUT  L8_PIN_grpi;
      PIN  A0  IN  L8_PIN;
   END;  // SYM PRBUFOB

   SYM PGBUFI GRP_L8_PIN_grp  GRP;
      PIN  Z0  OUT  L8_PIN_grp;
      PIN  A0  IN  L8_PIN_grpi;
   END;  // SYM PRBUFO2

   SYM PGBUFI GRP_L8_PIN_iomux  GRP;
      PIN  Z0  OUT  L8_PIN_iomux;
      PIN  A0  IN  L8_PIN;
   END;  // SYM PRBUFX1

   SYM PGBUFI GRP_LEFTX_grp  GRP;
      PIN  Z0  OUT  LEFTX_grp;
      PIN  A0  IN  LEFTX;
   END;  // SYM PRBUFO3

   SYM PGBUFI GRP_RIGHTX_grp  GRP;
      PIN  Z0  OUT  RIGHTX_grp;
      PIN  A0  IN  RIGHTX;
   END;  // SYM PRBUFO4

   SYM PGBUFI GRP_W_grpi  GRP;
      PIN  Z0  OUT  W_grpi;
      PIN  A0  IN  W;
   END;  // SYM PRBUFOB

   SYM PGBUFI GRP_W_grp  GRP;
      PIN  Z0  OUT  W_grp;
      PIN  A0  IN  W_grpi;
   END;  // SYM PRBUFO3

   SYM PGBUFI GRP_W_ffb  GRP;
      PIN  Z0  OUT  W_ffb;
      PIN  A0  IN  W;
   END;  // SYM PGBUFF

   SYM PGBUFI GRP_W_D_grpi  GRP;
      PIN  Z0  OUT  W_D_grpi;
      PIN  A0  IN  W_D;
   END;  // SYM PRBUFOB

   SYM PGBUFI GRP_W_D_grp  GRP;
      PIN  Z0  OUT  W_D_grp;
      PIN  A0  IN  W_D_grpi;
   END;  // SYM PRBUFO3

   SYM PGBUFI GRP__AND_704_ffb  GRP;
      PIN  Z0  OUT  _AND_704_ffb;
      PIN  A0  IN  _AND_704;
   END;  // SYM PGBUFF

   SYM PGBUFI GRP__AND_704_grpi  GRP;
      PIN  Z0  OUT  _AND_704_grpi;
      PIN  A0  IN  _AND_704;
   END;  // SYM PRBUFOB

   SYM PGBUFI GRP__AND_704_grp  GRP;
      PIN  Z0  OUT  _AND_704_grp;
      PIN  A0  IN  _AND_704_grpi;
   END;  // SYM PRBUFO3

   SYM PGBUFI GRP_W_C_ck2f  GRP;
      PIN  Z0  OUT  W_C_ck2f;
      PIN  A0  IN  W_C;
   END;  // SYM PKBUFG2

   SYM PGBUFI GRP_W_C_clk2  GRP;
      PIN  Z0  OUT  W_C_clk2;
      PIN  A0  IN  W_C_ck2f;
   END;  // SYM PRBUFK2

   SYM PXIN GRP_RESET_glb  GRP;
      PIN  Z0  OUT  !RESET_glb;
      PIN  XI0  IN  !RESET;
   END;  // SYM PXINRG
END;  // PHYSSIM SECTION

SECTION INSTANCE_TIMING_DATA;

// File created on Thu May 26 21:18:32 2005


// Copyright (c) Lattice Semiconductor Corp. 1992. All rights reserved.