📄 bahe.sim
字号:
LAF 1.4.1 S;
SECTION HEADER;
DESIGN bahe 0.0;
END; // HEADER SECTION
SECTION DEVICE;
TECHNOLOGY ispLSI;
PART ispLSI1016E-80LJ44;
END; // DEVICE SECTION
SECTION PHYSSIM;
XPIN !XRESET IN !XRESET XTYPE RST LOCK 35;
XPIN RIGHT IN RIGHT XTYPE IO LOCK 22;
XPIN LEFT IN LEFT XTYPE IO LOCK 9;
XPIN CLR IN CLR XTYPE IO LOCK 21;
XPIN L8 OUT L8 XTYPE IO LOCK 16;
XPIN L7 OUT L7 XTYPE IO LOCK 25;
XPIN L6 OUT L6 XTYPE IO LOCK 17;
XPIN L5 OUT L5 XTYPE IO LOCK 30;
XPIN L4 OUT L4 XTYPE IO LOCK 43;
XPIN L3 OUT L3 XTYPE IO LOCK 31;
XPIN L2 OUT L2 XTYPE IO LOCK 10;
XPIN L1 OUT L1 XTYPE IO LOCK 32;
XPIN L0 OUT L0 XTYPE IO LOCK 28;
NET L2_PIN_buff1_grpi SRC GRP_L2_PIN_buff1_grpi.Z0 DST GRP_L2_PIN_buff1_grp.A0;
NET L2_PIN_grpi SRC GRP_L2_PIN_grpi.Z0 DST GRP_L2_PIN_grp.A0;
NET L7_PIN_grpi SRC GRP_L7_PIN_grpi.Z0 DST GRP_L7_PIN_grp.A0;
NET L5_PIN_grpi SRC GRP_L5_PIN_grpi.Z0 DST GRP_L5_PIN_grp.A0;
NET L3_PIN_grpi SRC GRP_L3_PIN_grpi.Z0 DST GRP_L3_PIN_grp.A0;
NET L1_PIN_grpi SRC GRP_L1_PIN_grpi.Z0 DST GRP_L1_PIN_grp.A0;
NET L0_PIN_grpi SRC GRP_L0_PIN_grpi.Z0 DST GRP_L0_PIN_grp.A0;
NET L4_PIN_grpi SRC GRP_L4_PIN_grpi.Z0 DST GRP_L4_PIN_grp.A0;
NET L6_PIN_grpi SRC GRP_L6_PIN_grpi.Z0 DST GRP_L6_PIN_grp.A0;
NET L8_PIN_grpi SRC GRP_L8_PIN_grpi.Z0 DST GRP_L8_PIN_grp.A0;
NET W_grpi SRC GRP_W_grpi.Z0 DST GRP_W_grp.A0;
NET W_D_grpi SRC GRP_W_D_grpi.Z0 DST GRP_W_D_grp.A0;
NET _AND_704_grpi SRC GRP__AND_704_grpi.Z0 DST GRP__AND_704_grp.A0;
NET W_C_ck2f SRC GRP_W_C_ck2f.Z0 DST GRP_W_C_clk2.A0;
NET !RESET SRC IOC_RESET.Z0 DST GRP_RESET_glb.XI0;
NET !XRESET EXT DST IOC_RESET.XI0;
NET RIGHT EXT DST IOC_IO7_IBUFO.XI0;
NET RIGHTX SRC IOC_RIGHTX.Z0 DST GRP_RIGHTX_grp.A0;
NET IO7_IBUFO SRC IOC_IO7_IBUFO.Z0 DST IOC_RIGHTX.A0;
NET LEFT EXT DST IOC_IO30_IBUFO.XI0;
NET LEFTX SRC IOC_LEFTX.Z0 DST GRP_LEFTX_grp.A0;
NET IO30_IBUFO SRC IOC_IO30_IBUFO.Z0 DST IOC_LEFTX.A0;
NET CLR EXT DST IOC_IO6_IBUFO.XI0;
NET CLRX SRC IOC_CLRX.Z0 DST GRP_CLRX_grp.A0;
NET IO6_IBUFO SRC IOC_IO6_IBUFO.Z0 DST IOC_CLRX.A0;
NET L8 EXT SRC IOC_L8.XO0;
NET IO1_OBUFI SRC IOC_IO1_OBUFI.Z0 DST IOC_L8.A0;
NET L8_PIN_iomux SRC GRP_L8_PIN_iomux.Z0 DST IOC_IO1_OBUFI.A0;
NET L7 EXT SRC IOC_L7.XO0;
NET IO8_OBUFI SRC IOC_IO8_OBUFI.Z0 DST IOC_L7.A0;
NET L7_PIN_iomux SRC GRP_L7_PIN_iomux.Z0 DST IOC_IO8_OBUFI.A0;
NET L6 EXT SRC IOC_L6.XO0;
NET IO2_OBUFI SRC IOC_IO2_OBUFI.Z0 DST IOC_L6.A0;
NET L6_PIN_iomux SRC GRP_L6_PIN_iomux.Z0 DST IOC_IO2_OBUFI.A0;
NET L5 EXT SRC IOC_L5.XO0;
NET IO13_OBUFI SRC IOC_IO13_OBUFI.Z0 DST IOC_L5.A0;
NET L5_PIN_iomux SRC GRP_L5_PIN_iomux.Z0 DST IOC_IO13_OBUFI.A0;
NET L4 EXT SRC IOC_L4.XO0;
NET IO22_OBUFI SRC IOC_IO22_OBUFI.Z0 DST IOC_L4.A0;
NET L4_PIN_iomux SRC GRP_L4_PIN_iomux.Z0 DST IOC_IO22_OBUFI.A0;
NET L3 EXT SRC IOC_L3.XO0;
NET IO14_OBUFI SRC IOC_IO14_OBUFI.Z0 DST IOC_L3.A0;
NET L3_PIN_iomux SRC GRP_L3_PIN_iomux.Z0 DST IOC_IO14_OBUFI.A0;
NET L2 EXT SRC IOC_L2.XO0;
NET IO31_OBUFI SRC IOC_IO31_OBUFI.Z0 DST IOC_L2.A0;
NET L2_PIN_iomux SRC GRP_L2_PIN_iomux.Z0 DST IOC_IO31_OBUFI.A0;
NET L1 EXT SRC IOC_L1.XO0;
NET IO15_OBUFI SRC IOC_IO15_OBUFI.Z0 DST IOC_L1.A0;
NET L1_PIN_iomux SRC GRP_L1_PIN_iomux.Z0 DST IOC_IO15_OBUFI.A0;
NET L0 EXT SRC IOC_L0.XO0;
NET IO11_OBUFI SRC IOC_IO11_OBUFI.Z0 DST IOC_L0.A0;
NET L0_PIN_iomux SRC GRP_L0_PIN_iomux.Z0 DST IOC_IO11_OBUFI.A0;
NET A0_X1MO SRC GLB_A0_X1MO.Z0 DST GLB_A0_X1O.A1;
NET A0_P8_xa SRC GLB_A0_P8_xa.Z0 DST GLB_A0_X1MO.A0;
NET L2_PIN_buff1 SRC GLB_L2_PIN_buff1.Z0 DST GRP_L2_PIN_buff1_grpi.A0;
NET A0_X1O SRC GLB_A0_X1O.Z0 DST GLB_L2_PIN_buff1.A0;
NET A0_G2 SRC GLB_A0_G2.Z0 DST GLB_A0_X1O.A0;
NET L2_PIN_grp SRC GRP_L2_PIN_grp.Z0 DST GLB_A0_IN3.A0;
NET A0_P8 SRC GLB_A0_P8.Z0 DST GLB_A0_P8_xa.A0;
NET A0_IN3 SRC GLB_A0_IN3.Z0 DST GLB_A0_P8.A0;
NET L1_PIN SRC GLB_L1_PIN.Q0 DST GRP_L1_PIN_grpi.A0 GRP_L1_PIN_iomux.A0;
NET L3_PIN SRC GLB_L3_PIN.Q0 DST GRP_L3_PIN_ffb.A0 GRP_L3_PIN_grpi.A0 GRP_L3_PIN_iomux.A0;
NET L5_PIN SRC GLB_L5_PIN.Q0 DST GRP_L5_PIN_ffb.A0 GRP_L5_PIN_grpi.A0 GRP_L5_PIN_iomux.A0;
NET L7_PIN SRC GLB_L7_PIN.Q0 DST GRP_L7_PIN_grpi.A0 GRP_L7_PIN_iomux.A0;
NET A1_CLK SRC GLB_A1_CLK.Z0 DST GLB_L1_PIN.CLK GLB_L3_PIN.CLK GLB_L5_PIN.CLK GLB_L7_PIN.CLK;
NET L1_PIN_D0 SRC GLB_L1_PIN_D0.Z0 DST GLB_L1_PIN.D0;
NET A1_X3O SRC GLB_A1_X3O.Z0 DST GLB_L1_PIN_D0.A0;
NET L3_PIN_D0 SRC GLB_L3_PIN_D0.Z0 DST GLB_L3_PIN.D0;
NET A1_X2O SRC GLB_A1_X2O.Z0 DST GLB_L3_PIN_D0.A0;
NET L5_PIN_D0 SRC GLB_L5_PIN_D0.Z0 DST GLB_L5_PIN.D0;
NET A1_X1O SRC GLB_A1_X1O.Z0 DST GLB_L5_PIN_D0.A0;
NET L7_PIN_D0 SRC GLB_L7_PIN_D0.Z0 DST GLB_L7_PIN.D0;
NET A1_X0O SRC GLB_A1_X0O.Z0 DST GLB_L7_PIN_D0.A0;
NET A1_G3 SRC GLB_A1_G3.Z0 DST GLB_A1_X0O.A0;
NET A1_G2 SRC GLB_A1_G2.Z0 DST GLB_A1_X1O.A0;
NET A1_G1 SRC GLB_A1_G1.Z0 DST GLB_A1_X2O.A0;
NET A1_G0 SRC GLB_A1_G0.Z0 DST GLB_A1_X3O.A0;
NET A1_F5 SRC GLB_A1_F5.Z0 DST GLB_A1_G0.A0;
NET A1_F4 SRC GLB_A1_F4.Z0 DST GLB_A1_G1.A0;
NET A1_F1 SRC GLB_A1_F1.Z0 DST GLB_A1_G2.A0;
NET A1_F0 SRC GLB_A1_F0.Z0 DST GLB_A1_G3.A0;
NET A1_P16 SRC GLB_A1_P16.Z0 DST GLB_A1_F5.A0;
NET A1_IN7 SRC GLB_A1_IN7.Z0 DST GLB_A1_P16.A0;
NET A1_P15 SRC GLB_A1_P15.Z0 DST GLB_A1_F5.A1;
NET A1_IN0 SRC GLB_A1_IN0.Z0 DST GLB_A1_P15.A5;
NET A1_P14 SRC GLB_A1_P14.Z0 DST GLB_A1_F5.A2;
NET L3_PIN_ffb SRC GRP_L3_PIN_ffb.Z0 DST GLB_A1_IN17.A0;
NET A1_P12 SRC GLB_A1_P12.Z0 DST GLB_A1_F4.A0;
NET A1_IN17 SRC GLB_A1_IN17.Z0 DST GLB_A1_P12.A0;
NET A1_P11 SRC GLB_A1_P11.Z0 DST GLB_A1_F4.A1;
NET L2_PIN_buff1_grp SRC GRP_L2_PIN_buff1_grp.Z0 DST GLB_A1_IN5.A0;
NET A1_P10 SRC GLB_A1_P10.Z0 DST GLB_A1_F4.A2;
NET A1_IN5 SRC GLB_A1_IN5.Z0 DST GLB_A1_P14.A4 GLB_A1_P11.A4 GLB_A1_P10.A3;
NET A1_P9 SRC GLB_A1_P9.Z0 DST GLB_A1_F4.A3;
NET L5_PIN_ffb SRC GRP_L5_PIN_ffb.Z0 DST GLB_A1_IN16.A0;
NET A1_P7 SRC GLB_A1_P7.Z0 DST GLB_A1_F1.A0;
NET A1_IN16 SRC GLB_A1_IN16.Z0 DST GLB_A1_P7.A0;
NET A1_P6 SRC GLB_A1_P6.Z0 DST GLB_A1_F1.A1;
NET L4_PIN_grp SRC GRP_L4_PIN_grp.Z0 DST GLB_A1_IN6.A0;
NET A1_P5 SRC GLB_A1_P5.Z0 DST GLB_A1_F1.A2;
NET A1_IN6 SRC GLB_A1_IN6.Z0 DST GLB_A1_P9.A4 GLB_A1_P6.A4 GLB_A1_P5.A3;
NET A1_P4 SRC GLB_A1_P4.Z0 DST GLB_A1_F1.A3;
NET A1_IN8B SRC GLB_A1_IN8B.ZN0 DST GLB_A1_P14.A3 GLB_A1_P9.A3 GLB_A1_P4.A3;
NET A1_P3 SRC GLB_A1_P3.Z0 DST GLB_A1_F0.A0;
NET A1_IN3 SRC GLB_A1_IN3.Z0 DST GLB_A1_P16.A1 GLB_A1_P12.A1 GLB_A1_P7.A1 GLB_A1_P3.A1;
NET A1_IN4 SRC GLB_A1_IN4.Z0 DST GLB_A1_P3.A0;
NET A1_P2 SRC GLB_A1_P2.Z0 DST GLB_A1_F0.A1;
NET A1_IN12B SRC GLB_A1_IN12B.ZN0 DST GLB_A1_P15.A1 GLB_A1_P11.A1 GLB_A1_P6.A1 GLB_A1_P2.A1;
NET A1_P1 SRC GLB_A1_P1.Z0 DST GLB_A1_F0.A2;
NET A1_IN2 SRC GLB_A1_IN2.Z0 DST GLB_A1_P1.A4;
NET A1_IN10B SRC GLB_A1_IN10B.ZN0 DST GLB_A1_P1.A2;
NET A1_IN12 SRC GLB_A1_IN12.Z0 DST GLB_A1_P14.A1 GLB_A1_P9.A1 GLB_A1_P4.A1 GLB_A1_P1.A1;
NET A1_P0 SRC GLB_A1_P0.Z0 DST GLB_A1_F0.A3;
NET A1_IN0B SRC GLB_A1_IN0B.ZN0 DST GLB_A1_P14.A5 GLB_A1_P10.A5 GLB_A1_P9.A5 GLB_A1_P5.A5 GLB_A1_P4.A5
GLB_A1_P1.A5 GLB_A1_P0.A5;
NET A1_IN1 SRC GLB_A1_IN1.Z0 DST GLB_A1_P4.A4 GLB_A1_P2.A5 GLB_A1_P0.A4;
NET A1_IN2B SRC GLB_A1_IN2B.ZN0 DST GLB_A1_P15.A4 GLB_A1_P11.A5 GLB_A1_P10.A4 GLB_A1_P6.A5 GLB_A1_P5.A4
GLB_A1_P2.A4 GLB_A1_P0.A3;
NET A1_IN9B SRC GLB_A1_IN9B.ZN0 DST GLB_A1_P15.A3 GLB_A1_P14.A2 GLB_A1_P11.A3 GLB_A1_P10.A2 GLB_A1_P9.A2
GLB_A1_P6.A3 GLB_A1_P5.A2 GLB_A1_P4.A2 GLB_A1_P2.A3 GLB_A1_P1.A3
GLB_A1_P0.A2;
NET A1_IN10 SRC GLB_A1_IN10.Z0 DST GLB_A1_P15.A2 GLB_A1_P11.A2 GLB_A1_P10.A1 GLB_A1_P6.A2 GLB_A1_P5.A1
GLB_A1_P2.A2 GLB_A1_P0.A1;
NET A1_IN13B SRC GLB_A1_IN13B.ZN0 DST GLB_A1_P15.A0 GLB_A1_P14.A0 GLB_A1_P11.A0 GLB_A1_P10.A0 GLB_A1_P9.A0
GLB_A1_P6.A0 GLB_A1_P5.A0 GLB_A1_P4.A0 GLB_A1_P2.A0 GLB_A1_P1.A0
GLB_A1_P0.A0;
NET L0_PIN SRC GLB_L0_PIN.Q0 DST GRP_L0_PIN_grpi.A0 GRP_L0_PIN_iomux.A0;
NET L6_PIN SRC GLB_L6_PIN.Q0 DST GRP_L6_PIN_grpi.A0 GRP_L6_PIN_iomux.A0;
NET L8_PIN SRC GLB_L8_PIN.Q0 DST GRP_L8_PIN_ffb.A0 GRP_L8_PIN_grpi.A0 GRP_L8_PIN_iomux.A0;
NET A6_CLK SRC GLB_A6_CLK.Z0 DST GLB_L0_PIN.CLK GLB_L6_PIN.CLK GLB_L8_PIN.CLK;
NET L0_PIN_D0 SRC GLB_L0_PIN_D0.Z0 DST GLB_L0_PIN.D0;
NET A6_X3O SRC GLB_A6_X3O.Z0 DST GLB_L0_PIN_D0.A0;
NET L6_PIN_D0 SRC GLB_L6_PIN_D0.Z0 DST GLB_L6_PIN.D0;
NET A6_X2O SRC GLB_A6_X2O.Z0 DST GLB_L6_PIN_D0.A0;
NET L8_PIN_D0 SRC GLB_L8_PIN_D0.Z0 DST GLB_L8_PIN.D0;
NET A6_X1O SRC GLB_A6_X1O.Z0 DST GLB_L8_PIN_D0.A0;
NET A6_X0MO SRC GLB_A6_X0MO.Z0 DST GLB_A6_X0O.A1;
NET A6_P13_xa SRC GLB_A6_P13_xa.Z0 DST GLB_A6_X0MO.A0;
NET _AND_704 SRC GLB__AND_704.Z0 DST GRP__AND_704_ffb.A0 GRP__AND_704_grpi.A0;
NET A6_X0O SRC GLB_A6_X0O.Z0 DST GLB__AND_704.A0;
NET A6_G3 SRC GLB_A6_G3.Z0 DST GLB_A6_X0O.A0;
NET A6_G2 SRC GLB_A6_G2.Z0 DST GLB_A6_X1O.A0;
NET A6_G1 SRC GLB_A6_G1.Z0 DST GLB_A6_X2O.A0;
NET A6_G0 SRC GLB_A6_G0.Z0 DST GLB_A6_X3O.A0;
NET A6_F4 SRC GLB_A6_F4.Z0 DST GLB_A6_G2.A0;
NET A6_F1 SRC GLB_A6_F1.Z0 DST GLB_A6_G0.A0;
NET A6_F0 SRC GLB_A6_F0.Z0 DST GLB_A6_G1.A0;
NET A6_P13 SRC GLB_A6_P13.Z0 DST GLB_A6_P13_xa.A0;
NET A6_P12 SRC GLB_A6_P12.Z0 DST GLB_A6_F4.A0;
NET A6_P11 SRC GLB_A6_P11.Z0 DST GLB_A6_F4.A1;
NET A6_P10 SRC GLB_A6_P10.Z0 DST GLB_A6_F4.A2;
NET A6_IN17 SRC GLB_A6_IN17.Z0 DST GLB_A6_P13.A0 GLB_A6_P11.A0 GLB_A6_P10.A0;
NET A6_P9 SRC GLB_A6_P9.Z0 DST GLB_A6_F4.A3;
NET A6_P8 SRC GLB_A6_P8.Z0 DST GLB_A6_F4.A4;
NET A6_P7 SRC GLB_A6_P7.Z0 DST GLB_A6_F1.A0;
NET A6_P6 SRC GLB_A6_P6.Z0 DST GLB_A6_F1.A1;
NET A6_IN2 SRC GLB_A6_IN2.Z0 DST GLB_A6_P11.A2 GLB_A6_P6.A1;
NET A6_P5 SRC GLB_A6_P5.Z0 DST GLB_A6_F1.A2;
NET A6_IN0 SRC GLB_A6_IN0.Z0 DST GLB_A6_P10.A3 GLB_A6_P7.A2 GLB_A6_P6.A2 GLB_A6_P5.A2;
NET A6_IN16 SRC GLB_A6_IN16.Z0 DST GLB_A6_P12.A0 GLB_A6_P5.A0;
NET A6_P4 SRC GLB_A6_P4.Z0 DST GLB_A6_F1.A3;
NET A6_IN7 SRC GLB_A6_IN7.Z0 DST GLB_A6_P4.A2;
NET L6_PIN_grp SRC GRP_L6_PIN_grp.Z0 DST GLB_A1_IN1.A0 GLB_A6_IN1.A0;
NET A6_P3 SRC GLB_A6_P3.Z0 DST GLB_A6_F0.A0;
NET A6_IN1 SRC GLB_A6_IN1.Z0 DST GLB_A6_P3.A1;
NET A6_IN3 SRC GLB_A6_IN3.Z0 DST GLB_A6_P3.A0;
NET A6_P2 SRC GLB_A6_P2.Z0 DST GLB_A6_F0.A1;
NET A6_IN12B SRC GLB_A6_IN12B.ZN0 DST GLB_A6_P9.A0 GLB_A6_P2.A1;
NET L8_PIN_ffb SRC GRP_L8_PIN_ffb.Z0 DST GLB_A6_IN17.A0 GLB_A6_IN17B.A0;
NET A6_P1 SRC GLB_A6_P1.Z0 DST GLB_A6_F0.A2;
NET A6_IN5 SRC GLB_A6_IN5.Z0 DST GLB_A6_P2.A4 GLB_A6_P1.A3;
NET A6_IN10 SRC GLB_A6_IN10.Z0 DST GLB_A6_P13.A1 GLB_A6_P9.A1 GLB_A6_P8.A0 GLB_A6_P2.A2 GLB_A6_P1.A1;
NET A6_IN17B SRC GLB_A6_IN17B.ZN0 DST GLB_A6_P2.A0 GLB_A6_P1.A0;
NET L7_PIN_grp SRC GRP_L7_PIN_grp.Z0 DST GLB_A1_IN4.A0 GLB_A6_IN4.A0;
NET _AND_704_ffb SRC GRP__AND_704_ffb.Z0 DST GLB_A6_IN16.A0 GLB_A6_IN16B.A0;
NET A6_P0 SRC GLB_A6_P0.Z0 DST GLB_A6_F0.A3;
NET A6_IN0B SRC GLB_A6_IN0B.ZN0 DST GLB_A6_P8.A4 GLB_A6_P1.A5 GLB_A6_P0.A5;
NET A6_IN2B SRC GLB_A6_IN2B.ZN0 DST GLB_A6_P9.A4 GLB_A6_P8.A3 GLB_A6_P4.A4 GLB_A6_P2.A5 GLB_A6_P1.A4
GLB_A6_P0.A4;
NET A6_IN4 SRC GLB_A6_IN4.Z0 DST GLB_A6_P9.A3 GLB_A6_P8.A2 GLB_A6_P0.A3;
NET A6_IN6B SRC GLB_A6_IN6B.ZN0 DST GLB_A6_P12.A1 GLB_A6_P11.A1 GLB_A6_P10.A2 GLB_A6_P9.A2 GLB_A6_P8.A1
GLB_A6_P7.A1 GLB_A6_P6.A0 GLB_A6_P5.A1 GLB_A6_P4.A3 GLB_A6_P2.A3
GLB_A6_P1.A2 GLB_A6_P0.A2;
NET A6_IN12 SRC GLB_A6_IN12.Z0 DST GLB_A6_P10.A1 GLB_A6_P7.A0 GLB_A6_P4.A1 GLB_A6_P0.A1;
NET A6_IN16B SRC GLB_A6_IN16B.ZN0 DST GLB_A6_P4.A0 GLB_A6_P0.A0;
NET L2_PIN SRC GLB_L2_PIN.Q0 DST GRP_L2_PIN_grpi.A0 GRP_L2_PIN_ffb.A0 GRP_L2_PIN_iomux.A0;
NET L4_PIN SRC GLB_L4_PIN.Q0 DST GRP_L4_PIN_grpi.A0 GRP_L4_PIN_ffb.A0 GRP_L4_PIN_iomux.A0;
NET B0_CLK SRC GLB_B0_CLK.Z0 DST GLB_L2_PIN.CLK GLB_L4_PIN.CLK;
NET L2_PIN_D0 SRC GLB_L2_PIN_D0.Z0 DST GLB_L2_PIN.D0;
NET B0_X3O SRC GLB_B0_X3O.Z0 DST GLB_L2_PIN_D0.A0;
NET L4_PIN_D0 SRC GLB_L4_PIN_D0.Z0 DST GLB_L4_PIN.D0;
NET B0_X2O SRC GLB_B0_X2O.Z0 DST GLB_L4_PIN_D0.A0;
NET W_C SRC GLB_W_C.Z0 DST GRP_W_C_ck2f.A0;
NET B0_X1O SRC GLB_B0_X1O.Z0 DST GLB_W_C.A0;
NET B0_G2 SRC GLB_B0_G2.Z0 DST GLB_B0_X1O.A0;
NET B0_G1 SRC GLB_B0_G1.Z0 DST GLB_B0_X2O.A0;
NET B0_G0 SRC GLB_B0_G0.Z0 DST GLB_B0_X3O.A0;
NET B0_F5 SRC GLB_B0_F5.Z0 DST GLB_B0_G1.A0;
NET B0_F1 SRC GLB_B0_F1.Z0 DST GLB_B0_G2.A0;
NET B0_F0 SRC GLB_B0_F0.Z0 DST GLB_B0_G0.A0;
NET B0_P19 SRC GLB_B0_P19.Z0 DST GLB_B0_F5.A2;
NET B0_P18 SRC GLB_B0_P18.Z0 DST GLB_B0_F5.A0;
NET L5_PIN_grp SRC GRP_L5_PIN_grp.Z0 DST GLB_A6_IN5.A0 GLB_B0_IN10.A0;
NET B0_P17 SRC GLB_B0_P17.Z0 DST GLB_B0_F5.A1;
NET B0_IN10 SRC GLB_B0_IN10.Z0 DST GLB_B0_P17.A1;
NET B0_P16 SRC GLB_B0_P16.Z0 DST GLB_B0_F5.A3;
NET B0_IN9 SRC GLB_B0_IN9.Z0 DST GLB_B0_P16.A0;
NET B0_P15 SRC GLB_B0_P15.Z0 DST GLB_B0_F5.A4;
NET B0_IN6 SRC GLB_B0_IN6.Z0 DST GLB_B0_P15.A1;
NET B0_P14 SRC GLB_B0_P14.Z0 DST GLB_B0_F5.A5;
NET B0_IN7 SRC GLB_B0_IN7.Z0 DST GLB_B0_P14.A1;
NET L4_PIN_ffb SRC GRP_L4_PIN_ffb.Z0 DST GLB_B0_IN16.A0;
NET B0_P13 SRC GLB_B0_P13.Z0 DST GLB_B0_F5.A6;
NET B0_IN15 SRC GLB_B0_IN15.Z0 DST GLB_B0_P13.A1;
NET B0_IN16 SRC GLB_B0_IN16.Z0 DST GLB_B0_P15.A0 GLB_B0_P14.A0 GLB_B0_P13.A0;
NET B0_P7 SRC GLB_B0_P7.Z0 DST GLB_B0_F1.A0;
NET B0_P6 SRC GLB_B0_P6.Z0 DST GLB_B0_F1.A1;
NET L2_PIN_ffb SRC GRP_L2_PIN_ffb.Z0 DST GLB_B0_IN17.A0;
NET W_D_grp SRC GRP_W_D_grp.Z0 DST GLB_A1_IN3.A0 GLB_A6_IN3.A0 GLB_B0_IN12.A0;
NET B0_P3 SRC GLB_B0_P3.Z0 DST GLB_B0_F0.A0;
NET B0_IN12 SRC GLB_B0_IN12.Z0 DST GLB_B0_P3.A1;
NET B0_IN17 SRC GLB_B0_IN17.Z0 DST GLB_B0_P3.A0;
NET B0_P2 SRC GLB_B0_P2.Z0 DST GLB_B0_F0.A1;
NET B0_IN3B SRC GLB_B0_IN3B.ZN0 DST GLB_B0_P18.A3 GLB_B0_P2.A5;
NET L1_PIN_grp SRC GRP_L1_PIN_grp.Z0 DST GLB_A1_IN7.A0 GLB_A6_IN7.A0 GLB_B0_IN8.A0;
NET LEFTX_grp SRC GRP_LEFTX_grp.Z0 DST GLB_A1_IN10B.A0 GLB_A1_IN10.A0 GLB_A6_IN10.A0 GLB_B0_IN5.A0;
NET L8_PIN_grp SRC GRP_L8_PIN_grp.Z0 DST GLB_A1_IN2.A0 GLB_A1_IN2B.A0 GLB_B0_IN13B.A0;
NET B0_P1 SRC GLB_B0_P1.Z0 DST GLB_B0_F0.A2;
NET B0_IN5 SRC GLB_B0_IN5.Z0 DST GLB_B0_P19.A3 GLB_B0_P18.A2 GLB_B0_P6.A0 GLB_B0_P2.A4 GLB_B0_P1.A5;
NET B0_IN8 SRC GLB_B0_IN8.Z0 DST GLB_B0_P2.A2 GLB_B0_P1.A3;
NET B0_IN13B SRC GLB_B0_IN13B.ZN0 DST GLB_B0_P19.A1 GLB_B0_P18.A0 GLB_B0_P2.A0 GLB_B0_P1.A1;
NET L3_PIN_grp SRC GRP_L3_PIN_grp.Z0 DST GLB_B0_IN2.A0;
NET W_grp SRC GRP_W_grp.Z0 DST GLB_A1_IN9B.A0 GLB_A6_IN2.A0 GLB_A6_IN2B.A0 GLB_B0_IN6.A0 GLB_B0_IN6B.A0;
NET B0_P0 SRC GLB_B0_P0.Z0 DST GLB_B0_F0.A3;
NET B0_IN2 SRC GLB_B0_IN2.Z0 DST GLB_B0_P19.A4 GLB_B0_P18.A4 GLB_B0_P0.A5;
NET B0_IN3 SRC GLB_B0_IN3.Z0 DST GLB_B0_P17.A4 GLB_B0_P13.A2 GLB_B0_P7.A0 GLB_B0_P0.A4;
NET B0_IN6B SRC GLB_B0_IN6B.ZN0 DST GLB_B0_P19.A2 GLB_B0_P18.A1 GLB_B0_P17.A3 GLB_B0_P2.A3 GLB_B0_P1.A4
GLB_B0_P0.A3;
NET B0_IN7B SRC GLB_B0_IN7B.ZN0 DST GLB_B0_P17.A2 GLB_B0_P0.A2;
NET B0_IN9B SRC GLB_B0_IN9B.ZN0 DST GLB_B0_P2.A1 GLB_B0_P1.A2 GLB_B0_P0.A1;
NET B0_IN15B SRC GLB_B0_IN15B.ZN0 DST GLB_B0_P19.A0 GLB_B0_P17.A0 GLB_B0_P1.A0 GLB_B0_P0.A0;
NET W SRC GLB_W.Q0 DST GRP_W_grpi.A0 GRP_W_ffb.A0;
NET !RESET_glb SRC GRP_RESET_glb.Z0 DST GLB_L1_PIN.RNESET GLB_L3_PIN.RNESET GLB_L5_PIN.RNESET GLB_L7_PIN.RNESET GLB_L0_PIN.RNESET
GLB_L6_PIN.RNESET GLB_L8_PIN.RNESET GLB_L2_PIN.RNESET GLB_L4_PIN.RNESET GLB_W.RNESET;
NET GND DST GLB_A0_G2.A0 GLB_L1_PIN.CD GLB_L3_PIN.CD GLB_L5_PIN.CD GLB_L7_PIN.CD
GLB_A1_X3O.A1 GLB_A1_X2O.A1 GLB_A1_X1O.A1 GLB_A1_X0O.A1 GLB_L0_PIN.CD
GLB_L6_PIN.CD GLB_L8_PIN.CD GLB_A6_X3O.A1 GLB_A6_X2O.A1 GLB_A6_X1O.A1
GLB_A6_G3.A0 GLB_L2_PIN.CD GLB_L4_PIN.CD GLB_B0_X3O.A1 GLB_B0_X2O.A1
GLB_B0_X1O.A1 GLB_W.CD GLB_B6_X1O.A1 GLB_B6_X0O.A1;
NET B6_CLK SRC GLB_B6_CLK.Z0 DST GLB_W.CLK;
NET W_C_clk2 SRC GRP_W_C_clk2.Z0 DST GLB_A1_CLK.A0 GLB_A6_CLK.A0 GLB_B0_CLK.A0 GLB_B6_CLK.A0;
NET W_D0 SRC GLB_W_D0.Z0 DST GLB_W.D0;
NET B6_X1O SRC GLB_B6_X1O.Z0 DST GLB_W_D0.A0;
NET W_D SRC GLB_W_D.Z0 DST GRP_W_D_grpi.A0;
NET B6_X0O SRC GLB_B6_X0O.Z0 DST GLB_W_D.A0;
NET B6_G3 SRC GLB_B6_G3.Z0 DST GLB_B6_X0O.A0;
NET B6_G2 SRC GLB_B6_G2.Z0 DST GLB_B6_X1O.A0;
NET B6_F0 SRC GLB_B6_F0.Z0 DST GLB_B6_G3.A0 GLB_B6_G2.A0;
NET W_ffb SRC GRP_W_ffb.Z0 DST GLB_B6_IN16.A0;
NET B6_P3 SRC GLB_B6_P3.Z0 DST GLB_B6_F0.A0;
NET B6_IN16 SRC GLB_B6_IN16.Z0 DST GLB_B6_P3.A0;
NET _AND_704_grp SRC GRP__AND_704_grp.Z0 DST GLB_A1_IN8B.A0 GLB_B0_IN7.A0 GLB_B0_IN7B.A0 GLB_B6_IN12.A0;
NET B6_P2 SRC GLB_B6_P2.Z0 DST GLB_B6_F0.A1;
NET B6_IN12 SRC GLB_B6_IN12.Z0 DST GLB_B6_P2.A0;
NET L0_PIN_grp SRC GRP_L0_PIN_grp.Z0 DST GLB_A1_IN0.A0 GLB_A1_IN0B.A0 GLB_A6_IN0.A0 GLB_A6_IN0B.A0 GLB_B0_IN15.A0
GLB_B0_IN15B.A0 GLB_B6_IN15.A0;
NET RIGHTX_grp SRC GRP_RIGHTX_grp.Z0 DST GLB_A1_IN12B.A0 GLB_A1_IN12.A0 GLB_A6_IN12B.A0 GLB_A6_IN12.A0 GLB_B0_IN3B.A0
GLB_B0_IN3.A0 GLB_B6_IN8.A0;
NET CLRX_grp SRC GRP_CLRX_grp.Z0 DST GLB_A1_IN13B.A0 GLB_A6_IN6B.A0 GLB_B0_IN9.A0 GLB_B0_IN9B.A0 GLB_B6_IN9B.A0;
NET B6_P1 SRC GLB_B6_P1.Z0 DST GLB_B6_F0.A2;
NET B6_IN8 SRC GLB_B6_IN8.Z0 DST GLB_B6_P1.A2;
NET B6_IN9B SRC GLB_B6_IN9B.ZN0 DST GLB_B6_P3.A1 GLB_B6_P2.A1 GLB_B6_P1.A1;
NET B6_IN15 SRC GLB_B6_IN15.Z0 DST GLB_B6_P1.A0;
SYM PGBUFI GLB_A0_P8 GLB glb4;
PIN Z0 OUT A0_P8;
PIN A0 IN A0_IN3;
END; // SYM PGANDD1
SYM PGBUFI GLB_A0_G2 GLB glb4;
PIN Z0 OUT A0_G2;
PIN A0 IN GND;
END; // SYM PGORG1
SYM PGBUFI GLB_A0_P8_xa GLB glb4;
PIN Z0 OUT A0_P8_xa;
PIN A0 IN A0_P8;
END; // SYM PGBUFXA
SYM PGBUFI GLB_A0_X1MO GLB glb4;
PIN Z0 OUT A0_X1MO;
PIN A0 IN A0_P8_xa;
END; // SYM PGBUFXI
SYM PGBUFI GLB_L2_PIN_buff1 GLB glb4;
PIN Z0 OUT L2_PIN_buff1;
PIN A0 IN A0_X1O;
END; // SYM PGBUFXO
SYM PGBUFI GLB_A0_IN3 GLB glb4;
PIN Z0 OUT A0_IN3;
PIN A0 IN L2_PIN_grp;
END; // SYM PGBUFI
SYM PGXOR2 GLB_A0_X1O GLB glb4;
PIN Z0 OUT A0_X1O;
PIN A1 IN A0_X1MO;
PIN A0 IN A0_G2;
END; // SYM PGXOR2
SYM PGAND2 GLB_A1_P16 GLB glb02;
PIN Z0 OUT A1_P16;
PIN A1 IN A1_IN3;
PIN A0 IN A1_IN7;
END; // SYM PGAND2
SYM PGAND6 GLB_A1_P15 GLB glb02;
PIN Z0 OUT A1_P15;
PIN A5 IN A1_IN0;
PIN A4 IN A1_IN2B;
PIN A3 IN A1_IN9B;
PIN A2 IN A1_IN10;
PIN A1 IN A1_IN12B;
PIN A0 IN A1_IN13B;
END; // SYM PGAND6
SYM PGAND6 GLB_A1_P14 GLB glb02;
PIN Z0 OUT A1_P14;
PIN A5 IN A1_IN0B;
PIN A4 IN A1_IN5;
PIN A3 IN A1_IN8B;
PIN A2 IN A1_IN9B;
PIN A1 IN A1_IN12;
PIN A0 IN A1_IN13B;
END; // SYM PGAND6
SYM PGAND2 GLB_A1_P12 GLB glb02;
PIN Z0 OUT A1_P12;
PIN A1 IN A1_IN3;
PIN A0 IN A1_IN17;
END; // SYM PGANDD2
SYM PGAND6 GLB_A1_P11 GLB glb02;
PIN Z0 OUT A1_P11;
PIN A5 IN A1_IN2B;
PIN A4 IN A1_IN5;
PIN A3 IN A1_IN9B;
PIN A2 IN A1_IN10;
PIN A1 IN A1_IN12B;
PIN A0 IN A1_IN13B;
END; // SYM PGAND6
SYM PGAND6 GLB_A1_P10 GLB glb02;
PIN Z0 OUT A1_P10;
PIN A5 IN A1_IN0B;
PIN A4 IN A1_IN2B;
PIN A3 IN A1_IN5;
PIN A2 IN A1_IN9B;
PIN A1 IN A1_IN10;
PIN A0 IN A1_IN13B;
END; // SYM PGAND6
SYM PGAND6 GLB_A1_P9 GLB glb02;
PIN Z0 OUT A1_P9;
PIN A5 IN A1_IN0B;
PIN A4 IN A1_IN6;
PIN A3 IN A1_IN8B;
PIN A2 IN A1_IN9B;
PIN A1 IN A1_IN12;
PIN A0 IN A1_IN13B;
END; // SYM PGAND6
SYM PGAND2 GLB_A1_P7 GLB glb02;
PIN Z0 OUT A1_P7;
PIN A1 IN A1_IN3;
PIN A0 IN A1_IN16;
END; // SYM PGAND2
SYM PGAND6 GLB_A1_P6 GLB glb02;
PIN Z0 OUT A1_P6;
PIN A5 IN A1_IN2B;
PIN A4 IN A1_IN6;
PIN A3 IN A1_IN9B;
PIN A2 IN A1_IN10;
PIN A1 IN A1_IN12B;
PIN A0 IN A1_IN13B;
END; // SYM PGAND6
SYM PGAND6 GLB_A1_P5 GLB glb02;
PIN Z0 OUT A1_P5;
PIN A5 IN A1_IN0B;
PIN A4 IN A1_IN2B;
PIN A3 IN A1_IN6;
PIN A2 IN A1_IN9B;
PIN A1 IN A1_IN10;
PIN A0 IN A1_IN13B;
END; // SYM PGAND6
SYM PGAND6 GLB_A1_P4 GLB glb02;
PIN Z0 OUT A1_P4;
PIN A5 IN A1_IN0B;
PIN A4 IN A1_IN1;
PIN A3 IN A1_IN8B;
PIN A2 IN A1_IN9B;
PIN A1 IN A1_IN12;
PIN A0 IN A1_IN13B;
END; // SYM PGANDD6
SYM PGAND2 GLB_A1_P3 GLB glb02;
PIN Z0 OUT A1_P3;
PIN A1 IN A1_IN3;
PIN A0 IN A1_IN4;
END; // SYM PGAND2
SYM PGAND6 GLB_A1_P2 GLB glb02;
PIN Z0 OUT A1_P2;
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