bahe.laf

电子拔河游戏的实现, 二极管,移位寄存器和计数器的实现

LAF 11.0.5 L;

SECTION HEADER;
	DESIGN bahe 1.0.0;
	DESCRIPTION 拔河游戏机;
END;

SECTION DEVICE;
	TECHNOLOGY ispLSI;
	PART ispLSI1016E-80LJ44;
END;

SECTION LOGICAL;
XPIN LEFT IN LEFT LOCK 9;
XPIN RIGHT IN RIGHT LOCK 22;
XPIN CLR IN CLR;
XPIN L8 OUT L8_PIN LOCK 16;
XPIN L7 OUT L7_PIN LOCK 25;
XPIN L6 OUT L6_PIN LOCK 17;
XPIN L5 OUT L5_PIN LOCK 30;
XPIN L4 OUT L4_PIN LOCK 43;
XPIN L3 OUT L3_PIN LOCK 31;
XPIN L2 OUT L2_PIN LOCK 10;
XPIN L1 OUT L1_PIN LOCK 32;
XPIN L0 OUT L0_PIN LOCK 28;

NET LEFT EXT DST L8_C.A0 L7_C.A0 L6_C.A0 L5_C.A0 L4_C.A0
 L3_C.A0 L2_C.A0 L1_C.A0 L0_C.A0 W_C.A0
 L8_D.A0 L7_D.A0 L6_D.A0 L5_D.A0 L4_D.A0
 L3_D.A0 L2_D.A0 L1_D.A0 L0_D.A0 W_D.A0;

NET RIGHT EXT DST L8_C.A1 L7_C.A1 L6_C.A1 L5_C.A1 L4_C.A1
 L3_C.A1 L2_C.A1 L1_C.A1 L0_C.A1 W_C.A1
 L8_D.A1 L7_D.A1 L6_D.A1 L5_D.A1 L4_D.A1
 L3_D.A1 L2_D.A1 L1_D.A1 L0_D.A1 W_D.A1;

NET CLR EXT DST L8_D.A2 L7_D.A2 L6_D.A2 L5_D.A2 L4_D.A2
 L3_D.A2 L2_D.A2 L1_D.A2 L0_D.A2 W_D.A2;

NET L8_C SRC L8_C.Z0 DST L8.CLK;

NET L8_D SRC L8_D.Z0 DST L8.D0;

NET L8_PIN EXT SRC L8.Q0 DST L8_D.A3 L7_D.A3 L6_D.A3 L5_D.A3 L4_D.A3
 L3_D.A3 L2_D.A3 L1_D.A3 L0_D.A3 W_D.A3;

NET L7_C SRC L7_C.Z0 DST L7.CLK;

NET L7_D SRC L7_D.Z0 DST L7.D0;

NET L7_PIN EXT SRC L7.Q0 DST L8_D.A6 L7_D.A6 L6_D.A6;

NET L6_C SRC L6_C.Z0 DST L6.CLK;

NET L6_D SRC L6_D.Z0 DST L6.D0;

NET L6_PIN EXT SRC L6.Q0 DST L7_D.A7 L6_D.A7 L5_D.A6;

NET L5_C SRC L5_C.Z0 DST L5.CLK;

NET L5_D SRC L5_D.Z0 DST L5.D0;

NET L5_PIN EXT SRC L5.Q0 DST L6_D.A8 L5_D.A7 L4_D.A6;

NET L4_C SRC L4_C.Z0 DST L4.CLK;

NET L4_D SRC L4_D.Z0 DST L4.D0;

NET L4_PIN EXT SRC L4.Q0 DST L5_D.A8 L4_D.A7 L3_D.A6;

NET L3_C SRC L3_C.Z0 DST L3.CLK;

NET L3_D SRC L3_D.Z0 DST L3.D0;

NET L3_PIN EXT SRC L3.Q0 DST L4_D.A8 L3_D.A7 L2_D.A6;

NET L2_C SRC L2_C.Z0 DST L2.CLK;

NET L2_D SRC L2_D.Z0 DST L2.D0;

NET L2_PIN EXT SRC L2.Q0 DST L3_D.A8 L2_D.A7 L1_D.A6;

NET L1_C SRC L1_C.Z0 DST L1.CLK;

NET L1_D SRC L1_D.Z0 DST L1.D0;

NET L1_PIN EXT SRC L1.Q0 DST L2_D.A8 L1_D.A7 L0_D.A6;

NET L0_C SRC L0_C.Z0 DST L0.CLK;

NET L0_D SRC L0_D.Z0 DST L0.D0;

NET L0_PIN EXT SRC L0.Q0 DST L8_D.A4 L7_D.A4 L6_D.A4 L5_D.A4 L4_D.A4
 L3_D.A4 L2_D.A4 L1_D.A4 L0_D.A4 W_D.A4;

NET W_C SRC W_C.Z0 DST W.CLK;

NET W_D SRC W_D.Z0 DST W.D0;

NET W SRC W.Q0 DST L8_D.A5 L7_D.A5 L6_D.A5 L5_D.A5 L4_D.A5
 L3_D.A5 L2_D.A5 L1_D.A5 L0_D.A5 W_D.A5;

SYM PLA L8_C;
	PIN A0 IN LEFT;
	PIN A1 IN RIGHT;
	PIN Z0 OUT L8_C;
	BEGIN_PLA
	1- 1
	-1 1
	END_PLA
END;

SYM PLA L7_C;
	PIN A0 IN LEFT;
	PIN A1 IN RIGHT;
	PIN Z0 OUT L7_C;
	BEGIN_PLA
	1- 1
	-1 1
	END_PLA
END;

SYM PLA L6_C;
	PIN A0 IN LEFT;
	PIN A1 IN RIGHT;
	PIN Z0 OUT L6_C;
	BEGIN_PLA
	1- 1
	-1 1
	END_PLA
END;

SYM PLA L5_C;
	PIN A0 IN LEFT;
	PIN A1 IN RIGHT;
	PIN Z0 OUT L5_C;
	BEGIN_PLA
	1- 1
	-1 1
	END_PLA
END;

SYM PLA L4_C;
	PIN A0 IN LEFT;
	PIN A1 IN RIGHT;
	PIN Z0 OUT L4_C;
	BEGIN_PLA
	1- 1
	-1 1
	END_PLA
END;

SYM PLA L3_C;
	PIN A0 IN LEFT;
	PIN A1 IN RIGHT;
	PIN Z0 OUT L3_C;
	BEGIN_PLA
	1- 1
	-1 1
	END_PLA
END;

SYM PLA L2_C;
	PIN A0 IN LEFT;
	PIN A1 IN RIGHT;
	PIN Z0 OUT L2_C;
	BEGIN_PLA
	1- 1
	-1 1
	END_PLA
END;

SYM PLA L1_C;
	PIN A0 IN LEFT;
	PIN A1 IN RIGHT;
	PIN Z0 OUT L1_C;
	BEGIN_PLA
	1- 1
	-1 1
	END_PLA
END;

SYM PLA L0_C;
	PIN A0 IN LEFT;
	PIN A1 IN RIGHT;
	PIN Z0 OUT L0_C;
	BEGIN_PLA
	1- 1
	-1 1
	END_PLA
END;

SYM PLA W_C;
	PIN A0 IN LEFT;
	PIN A1 IN RIGHT;
	PIN Z0 OUT W_C;
	BEGIN_PLA
	1- 1
	-1 1
	END_PLA
END;

SYM PLA L8_D;
	PIN A0 IN LEFT;
	PIN A1 IN RIGHT;
	PIN A2 IN CLR;
	PIN A3 IN L8_PIN;
	PIN A4 IN L0_PIN;
	PIN A5 IN W;
	PIN A6 IN L7_PIN;
	PIN Z0 OUT L8_D;
	BEGIN_PLA
	1-01--- 1
	-1011-- 1
	--01-1- 1
	100--01 1
	1-0-001 1
	END_PLA
END;

SYM PLA L7_D;
	PIN A0 IN LEFT;
	PIN A1 IN RIGHT;
	PIN A2 IN CLR;
	PIN A3 IN L8_PIN;
	PIN A4 IN L0_PIN;
	PIN A5 IN W;
	PIN A6 IN L7_PIN;
	PIN A7 IN L6_PIN;
	PIN Z0 OUT L7_D;
	BEGIN_PLA
	010100-- 1
	1-01--1- 1
	-10-1-1- 1
	--0--11- 1
	1000-0-1 1
	1-0000-1 1
	END_PLA
END;

SYM PLA L6_D;
	PIN A0 IN LEFT;
	PIN A1 IN RIGHT;
	PIN A2 IN CLR;
	PIN A3 IN L8_PIN;
	PIN A4 IN L0_PIN;
	PIN A5 IN W;
	PIN A6 IN L7_PIN;
	PIN A7 IN L6_PIN;
	PIN A8 IN L5_PIN;
	PIN Z0 OUT L6_D;
	BEGIN_PLA
	010-001-- 1
	-100001-- 1
	1-01---1- 1
	-10-1--1- 1
	--0--1-1- 1
	1000-0--1 1
	1-0000--1 1
	END_PLA
END;

SYM PLA L5_D;
	PIN A0 IN LEFT;
	PIN A1 IN RIGHT;
	PIN A2 IN CLR;
	PIN A3 IN L8_PIN;
	PIN A4 IN L0_PIN;
	PIN A5 IN W;
	PIN A6 IN L6_PIN;
	PIN A7 IN L5_PIN;
	PIN A8 IN L4_PIN;
	PIN Z0 OUT L5_D;
	BEGIN_PLA
	010-001-- 1
	-100001-- 1
	1-01---1- 1
	-10-1--1- 1
	--0--1-1- 1
	1000-0--1 1
	1-0000--1 1
	END_PLA
END;

SYM PLA L4_D;
	PIN A0 IN LEFT;
	PIN A1 IN RIGHT;
	PIN A2 IN CLR;
	PIN A3 IN L8_PIN;
	PIN A4 IN L0_PIN;
	PIN A5 IN W;
	PIN A6 IN L5_PIN;
	PIN A7 IN L4_PIN;
	PIN A8 IN L3_PIN;
	PIN Z0 OUT L4_D;
	BEGIN_PLA
	--1------ 1
	01--001-- 1
	-1-0001-- 1
	1--1---1- 1
	-1--1--1- 1
	-----1-1- 1
	10-0-0--1 1
	1--000--1 1
	END_PLA
END;

SYM PLA L3_D;
	PIN A0 IN LEFT;
	PIN A1 IN RIGHT;
	PIN A2 IN CLR;
	PIN A3 IN L8_PIN;
	PIN A4 IN L0_PIN;
	PIN A5 IN W;
	PIN A6 IN L4_PIN;
	PIN A7 IN L3_PIN;
	PIN A8 IN L2_PIN;
	PIN Z0 OUT L3_D;
	BEGIN_PLA
	010-001-- 1
	-100001-- 1
	1-01---1- 1
	-10-1--1- 1
	--0--1-1- 1
	1000-0--1 1
	1-0000--1 1
	END_PLA
END;

SYM PLA L2_D;
	PIN A0 IN LEFT;
	PIN A1 IN RIGHT;
	PIN A2 IN CLR;
	PIN A3 IN L8_PIN;
	PIN A4 IN L0_PIN;
	PIN A5 IN W;
	PIN A6 IN L3_PIN;
	PIN A7 IN L2_PIN;
	PIN A8 IN L1_PIN;
	PIN Z0 OUT L2_D;
	BEGIN_PLA
	010-001-- 1
	-100001-- 1
	1-01---1- 1
	-10-1--1- 1
	--0--1-1- 1
	1000-0--1 1
	1-0000--1 1
	END_PLA
END;

SYM PLA L1_D;
	PIN A0 IN LEFT;
	PIN A1 IN RIGHT;
	PIN A2 IN CLR;
	PIN A3 IN L8_PIN;
	PIN A4 IN L0_PIN;
	PIN A5 IN W;
	PIN A6 IN L2_PIN;
	PIN A7 IN L1_PIN;
	PIN Z0 OUT L1_D;
	BEGIN_PLA
	100010-- 1
	010-001- 1
	-100001- 1
	1-01---1 1
	-10-1--1 1
	--0--1-1 1
	END_PLA
END;

SYM PLA L0_D;
	PIN A0 IN LEFT;
	PIN A1 IN RIGHT;
	PIN A2 IN CLR;
	PIN A3 IN L8_PIN;
	PIN A4 IN L0_PIN;
	PIN A5 IN W;
	PIN A6 IN L1_PIN;
	PIN Z0 OUT L0_D;
	BEGIN_PLA
	-10-1-- 1
	1-011-- 1
	--0-11- 1
	010--01 1
	-100-01 1
	END_PLA
END;

SYM PLA W_D;
	PIN A0 IN LEFT;
	PIN A1 IN RIGHT;
	PIN A2 IN CLR;
	PIN A3 IN L8_PIN;
	PIN A4 IN L0_PIN;
	PIN A5 IN W;
	PIN Z0 OUT W_D;
	BEGIN_PLA
	1-01-- 1
	-10-1- 1
	--0--1 1
	END_PLA
END;

SYM FD11 L8;
	PIN D0 IN L8_D;
	PIN CLK IN L8_C;
	PIN Q0 OUT L8_PIN;
END;

SYM FD11 L7;
	PIN D0 IN L7_D;
	PIN CLK IN L7_C;
	PIN Q0 OUT L7_PIN;
END;

SYM FD11 L6;
	PIN D0 IN L6_D;
	PIN CLK IN L6_C;
	PIN Q0 OUT L6_PIN;
END;

SYM FD11 L5;
	PIN D0 IN L5_D;
	PIN CLK IN L5_C;
	PIN Q0 OUT L5_PIN;
END;

SYM FD11 L4;
	PIN D0 IN L4_D;
	PIN CLK IN L4_C;
	PIN Q0 OUT L4_PIN;
END;

SYM FD11 L3;
	PIN D0 IN L3_D;
	PIN CLK IN L3_C;
	PIN Q0 OUT L3_PIN;
END;

SYM FD11 L2;
	PIN D0 IN L2_D;
	PIN CLK IN L2_C;
	PIN Q0 OUT L2_PIN;
END;

SYM FD11 L1;
	PIN D0 IN L1_D;
	PIN CLK IN L1_C;
	PIN Q0 OUT L1_PIN;
END;

SYM FD11 L0;
	PIN D0 IN L0_D;
	PIN CLK IN L0_C;
	PIN Q0 OUT L0_PIN;
END;

SYM FD11 W;
	PIN D0 IN W_D;
	PIN CLK IN W_C;
	PIN Q0 OUT W;
END;

END;

END;