📄 bahe.rpt
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ispEXPERT Compiler Release 7.0.15, Nov 4 1998 14:24:11
Design Parameters
-----------------
IGNORE_FIXED_PIN: OFF
MAX_GLB_IN: 16
MAX_GLB_OUT: 4
OS_VERSION: Windows 98
RESERVE_PIN_FILE: bahe.rsp
STRATEGY: AREA
TIMING_ANALYZER: OFF
Design Specification
--------------------
Design: bahe
Part: ispLSI1016E-80LJ44
Y1_AS_RESET: ON
Number of Critical Pins: 0
Number of Free Pins: 1
Number of Locked Pins: 11
Number of Reserved Pins: 0
Input Pins
Pin Name Pin Attribute
CLR PULLUP
LEFT LOCK 9, PULLUP
RIGHT LOCK 22, PULLUP
Output Pins
Pin Name Pin Attribute
L0 LOCK 28, PULLUP
L1 LOCK 32, PULLUP
L2 LOCK 10, PULLUP
L3 LOCK 31, PULLUP
L4 LOCK 43, PULLUP
L5 LOCK 30, PULLUP
L6 LOCK 17, PULLUP
L7 LOCK 25, PULLUP
L8 LOCK 16, PULLUP
Pre-Route Design Statistics
---------------------------
Number of Macrocells: 13
Number of GLBs: 4
Number of I/Os: 12
Number of Nets: 15
Number of Free Inputs: 1
Number of Free Outputs: 0
Number of Free Three-States: 0
Number of Free Bidi's: 0
Number of Locked Input IOCs: 2
Number of Locked DIs: 0
Number of Locked Outputs: 9
Number of Locked Three-States: 0
Number of Locked Bidi's: 0
Number of CRIT Outputs: 0
Number of Global OEs: 0
Number of External Clocks: 0
GLB Utilization (Out of 16): 25%
I/O Utilization (Out of 36): 33%
Net Utilization (Out of 100): 15%
Nets with Fanout of 3: 7
Nets with Fanout of 4: 7
Nets with Fanout of 5: 1
Average Fanout per Net: 3.60
GLBs with 5 Input(s): 1
GLBs with 12 Input(s): 1
GLBs with 13 Input(s): 1
GLBs with 15 Input(s): 1
Average Inputs per GLB: 11.25
GLBs with 2 Output(s): 1
GLBs with 3 Output(s): 1
GLBs with 4 Output(s): 2
Average Outputs per GLB: 3.25
Number of GLB Registers: 10
Number of IOC Registers: 0
Post-Route Design Implementation
--------------------------------
Number of Macrocells: 13
Number of GLBs: 5
Number of IOCs: 12
Number of DIs: 0
Number of GLB Levels: 3
GLB glb00, B6
5 Input(s)
(CLR.O, CLRX, I9), (glb03.O3, L0_PIN, I15), (RIGHT.O,
RIGHTX, I8), (glb00.O1, W, I16), (glb03.O0, _AND_704, I12)
2 Output(s)
(W_D, O0), (W, O1)
3 Product Term(s)
Output W_D
5 Input(s)
L0_PIN, RIGHTX, _AND_704, CLRX, W
3 Fanout(s)
glb02.I3, glb03.I3, glb01.I12
3 Product Term(s)
2 GLB Level(s)
W_D = (W & !CLRX
# _AND_704 & !CLRX
# L0_PIN & RIGHTX & !CLRX)
Output W
5 Input(s)
L0_PIN, RIGHTX, _AND_704, CLRX, W
4 Fanout(s)
glb02.I9, glb03.I2, glb01.I6, glb00.I16
3 Product Term(s)
2 GLB Level(s)
W.D = (W & !CLRX
# _AND_704 & !CLRX
# L0_PIN & RIGHTX & !CLRX)
W.C = W_C
Clock GLB glb01, B0
13 Input(s)
(CLR.O, CLRX, I9), (glb03.O3, L0_PIN, I15), (glb02.O3,
L1_PIN, I8), (glb01.O3, L2_PIN, I17), (glb02.O2, L3_PIN, I2),
(glb01.O2, L4_PIN, I16), (glb02.O1, L5_PIN, I10), (glb03.O1,
L8_PIN, I13), (LEFT.O, LEFTX, I5), (RIGHT.O, RIGHTX, I3),
(glb00.O1, W, I6), (glb00.O0, W_D, I12), (glb03.O0,
_AND_704, I7)
3 Output(s)
(W_C, O1), (L4_PIN, O2), (L2_PIN, O3)
13 Product Term(s)
Output W_C
2 Input(s)
LEFTX, RIGHTX
4 Fanout(s)
glb02.CLK2, glb03.CLK2, glb01.CLK2, glb00.CLK2
2 Product Term(s)
1 GLB Level(s)
W_C = (RIGHTX
# LEFTX)
Output L4_PIN
10 Input(s)
LEFTX, L3_PIN, L0_PIN, RIGHTX, L8_PIN, _AND_704, L5_PIN,
CLRX, L4_PIN, W
3 Fanout(s)
glb02.I6, glb01.I16, L4.IR
7 Product Term(s)
2 GLB Level(s)
L4_PIN.D = (CLRX
# L4_PIN & W
# L4_PIN & _AND_704
# L0_PIN & L4_PIN & RIGHTX
# L5_PIN & RIGHTX & !W & !_AND_704 & !L0_PIN
# L3_PIN & LEFTX & !L8_PIN & !W & !RIGHTX
# L3_PIN & LEFTX & !L8_PIN & !W & !L0_PIN)
L4_PIN.C = W_C
Output L2_PIN
11 Input(s)
LEFTX, L3_PIN, W_D, L0_PIN, RIGHTX, L8_PIN, _AND_704, L2_PIN,
CLRX, L1_PIN, W
3 Fanout(s)
glb4.I3, glb01.I17, L2.IR
4 Product Term(s)
3 GLB Level(s)
L2_PIN.D = (L2_PIN & W_D
# L1_PIN & LEFTX & !CLRX & !L8_PIN & !W & !RIGHTX
# L1_PIN & LEFTX & !CLRX & !L8_PIN & !W & !L0_PIN
# L3_PIN & RIGHTX & !CLRX & !W & !_AND_704 & !L0_PIN)
L2_PIN.C = W_C
GLB glb02, A1
15 Input(s)
(CLR.O, CLRX, I13), (glb03.O3, L0_PIN, I0), (glb02.O3,
L1_PIN, I7), (glb4.O1, L2_PIN_buff1, I5), (glb02.O2,
L3_PIN, I17), (glb01.O2, L4_PIN, I6), (glb02.O1, L5_PIN, I16),
(glb03.O2, L6_PIN, I1), (glb02.O0, L7_PIN, I4), (glb03.O1,
L8_PIN, I2), (LEFT.O, LEFTX, I10), (RIGHT.O, RIGHTX, I12),
(glb00.O1, W, I9), (glb00.O0, W_D, I3), (glb03.O0,
_AND_704, I8)
4 Output(s)
(L7_PIN, O0), (L5_PIN, O1), (L3_PIN, O2), (L1_PIN, O3)
15 Product Term(s)
Output L7_PIN
9 Input(s)
L6_PIN, LEFTX, W_D, L0_PIN, RIGHTX, L8_PIN, CLRX, L7_PIN, W
3 Fanout(s)
glb02.I4, glb03.I4, L7.IR
4 Product Term(s)
3 GLB Level(s)
L7_PIN.D = (L7_PIN & W_D
# L6_PIN & LEFTX & !CLRX & !L8_PIN & !W & !RIGHTX
# L8_PIN & RIGHTX & !CLRX & !W & !L0_PIN & !LEFTX
# L6_PIN & LEFTX & !CLRX & !L8_PIN & !W & !L0_PIN)
L7_PIN.C = W_C
Output L5_PIN
11 Input(s)
L6_PIN, LEFTX, W_D, L0_PIN, RIGHTX, L8_PIN, _AND_704, L5_PIN,
CLRX, L4_PIN, W
4 Fanout(s)
glb02.I16, glb03.I5, glb01.I10, L5.IR
4 Product Term(s)
3 GLB Level(s)
L5_PIN.D = (L5_PIN & W_D
# L4_PIN & LEFTX & !CLRX & !L8_PIN & !W & !RIGHTX
# L4_PIN & LEFTX & !CLRX & !L8_PIN & !W & !L0_PIN
# L6_PIN & RIGHTX & !CLRX & !W & !_AND_704 & !L0_PIN)
L5_PIN.C = W_C
Output L3_PIN
11 Input(s)
LEFTX, L3_PIN, W_D, L0_PIN, RIGHTX, L8_PIN, _AND_704,
L2_PIN_buff1, CLRX, L4_PIN, W
3 Fanout(s)
glb02.I17, glb01.I2, L3.IR
4 Product Term(s)
3 GLB Level(s)
L3_PIN.D = (L3_PIN & W_D
# L2_PIN_buff1 & LEFTX & !CLRX & !L8_PIN & !W & !RIGHTX
# L2_PIN_buff1 & LEFTX & !CLRX & !L8_PIN & !W & !L0_PIN
# L4_PIN & RIGHTX & !CLRX & !W & !_AND_704 & !L0_PIN)
L3_PIN.C = W_C
Output L1_PIN
10 Input(s)
LEFTX, W_D, L0_PIN, RIGHTX, L8_PIN, _AND_704, L2_PIN_buff1,
CLRX, L1_PIN, W
4 Fanout(s)
glb02.I7, glb03.I7, glb01.I8, L1.IR
3 Product Term(s)
3 GLB Level(s)
L1_PIN.D = (L1_PIN & W_D
# L0_PIN & LEFTX & !CLRX & !L8_PIN & !W & !RIGHTX
# L2_PIN_buff1 & RIGHTX & !CLRX & !W & !_AND_704 & !L0_PIN)
L1_PIN.C = W_C
GLB glb03, A6
12 Input(s)
(CLR.O, CLRX, I6), (glb03.O3, L0_PIN, I0), (glb02.O3,
L1_PIN, I7), (glb02.O1, L5_PIN, I5), (glb03.O2, L6_PIN, I1),
(glb02.O0, L7_PIN, I4), (glb03.O1, L8_PIN, I17), (LEFT.O,
LEFTX, I10), (RIGHT.O, RIGHTX, I12), (glb00.O1, W, I2),
(glb00.O0, W_D, I3), (glb03.O0, _AND_704, I16)
4 Output(s)
(_AND_704, O0), (L8_PIN, O1), (L6_PIN, O2), (L0_PIN, O3)
14 Product Term(s)
Output _AND_704
2 Input(s)
LEFTX, L8_PIN
4 Fanout(s)
glb02.I8, glb03.I16, glb01.I7, glb00.I12
1 Product Term(s)
1 GLB Level(s)
_AND_704 = L8_PIN & LEFTX
Output L8_PIN
8 Input(s)
LEFTX, L0_PIN, RIGHTX, L8_PIN, _AND_704, CLRX, L7_PIN, W
4 Fanout(s)
glb02.I2, glb03.I17, glb01.I13, L8.IR
5 Product Term(s)
2 GLB Level(s)
L8_PIN.D = (_AND_704 & !CLRX
# L8_PIN & W & !CLRX
# L0_PIN & L8_PIN & RIGHTX & !CLRX
# L7_PIN & LEFTX & !CLRX & !W & !RIGHTX
# L7_PIN & LEFTX & !CLRX & !W & !L0_PIN)
L8_PIN.C = W_C
Output L6_PIN
11 Input(s)
L6_PIN, LEFTX, W_D, L0_PIN, RIGHTX, L8_PIN, _AND_704, L5_PIN,
CLRX, L7_PIN, W
3 Fanout(s)
glb02.I1, glb03.I1, L6.IR
4 Product Term(s)
3 GLB Level(s)
L6_PIN.D = (L6_PIN & W_D
# L5_PIN & LEFTX & !CLRX & !L8_PIN & !W & !RIGHTX
# L5_PIN & LEFTX & !CLRX & !L8_PIN & !W & !L0_PIN
# L7_PIN & RIGHTX & !CLRX & !W & !_AND_704 & !L0_PIN)
L6_PIN.C = W_C
Output L0_PIN
6 Input(s)
L0_PIN, RIGHTX, _AND_704, CLRX, L1_PIN, W
5 Fanout(s)
glb02.I0, glb03.I0, glb01.I15, glb00.I15, L0.IR
4 Product Term(s)
2 GLB Level(s)
L0_PIN.D = (L0_PIN & RIGHTX & !CLRX
# L0_PIN & W & !CLRX
# L0_PIN & _AND_704 & !CLRX
# L1_PIN & RIGHTX & !CLRX & !W & !_AND_704)
L0_PIN.C = W_C
GLB glb4, A0
1 Input(s)
(glb01.O3, L2_PIN, I3)
1 Output(s)
(L2_PIN_buff1, O1)
1 Product Term(s)
Output L2_PIN_buff1
1 Input(s)
L2_PIN
1 Fanout(s)
glb02.I5
1 Product Term(s)
1 GLB Level(s)
L2_PIN_buff1 = L2_PIN
Input CLR, IO6
Output CLRX
4 Fanout(s)
glb02.I13, glb03.I6, glb01.I9, glb00.I9
Output L0, IO11
Input (glb03.O3, L0_PIN)
L0 = L0_PIN
Output L1, IO15
Input (glb02.O3, L1_PIN)
L1 = L1_PIN
Output L2, IO31
Input (glb01.O3, L2_PIN)
L2 = L2_PIN
Output L3, IO14
Input (glb02.O2, L3_PIN)
L3 = L3_PIN
Output L4, IO22
Input (glb01.O2, L4_PIN)
L4 = L4_PIN
Output L5, IO13
Input (glb02.O1, L5_PIN)
L5 = L5_PIN
Output L6, IO2
Input (glb03.O2, L6_PIN)
L6 = L6_PIN
Output L7, IO8
Input (glb02.O0, L7_PIN)
L7 = L7_PIN
Output L8, IO1
Input (glb03.O1, L8_PIN)
L8 = L8_PIN
Input LEFT, IO30
Output LEFTX
3 Fanout(s)
glb02.I10, glb03.I10, glb01.I5
Input RIGHT, IO7
Output RIGHTX
4 Fanout(s)
glb02.I12, glb03.I12, glb01.I3, glb00.I8
Clock Assignments
Net Name Clock Assignment
W_C Internal CLK2
GLB and GLB Output Statistics
GLB Name, Location GLB Statistics GLB Output Statistics
GLB Output Name Ins, Outs, PTs Ins, FOs, PTs, Levels
glb00, B6 5, 2, 3
W 0, 4, 3, 2
W_D 5, 3, 3, 2
glb01, B0 13, 3, 13
L2_PIN 11, 3, 4, 3
L4_PIN 10, 3, 7, 2
W_C 2, 4, 2, 1
glb02, A1 15, 4, 15
L1_PIN 10, 4, 3, 3
L3_PIN 11, 3, 4, 3
L5_PIN 11, 4, 4, 3
L7_PIN 9, 3, 4, 3
glb03, A6 12, 4, 14
L0_PIN 6, 5, 4, 2
L6_PIN 11, 3, 4, 3
L8_PIN 8, 4, 5, 2
_AND_704 2, 4, 1, 1
glb4, A0 1, 1, 1
L2_PIN_buff1 1, 1, 1, 1
Maximum-Level Trace
GLB Level, Name, Ins GLB Output Name
3, glb01, 9 L2_PIN
2, glb00 W_D
1, glb03 _AND_704
3, glb02, 8 L7_PIN
2, glb00 W_D
1, glb03 _AND_704
3, glb02, 9 L5_PIN
2, glb00 W_D
1, glb03 _AND_704
3, glb02, 9 L3_PIN
2, glb00 W_D
1, glb03 _AND_704
3, glb02, 8 L1_PIN
2, glb00 W_D
1, glb03 _AND_704
3, glb03, 9 L6_PIN
2, glb00 W_D
1, glb03 _AND_704
Pin Assignments
Pin Name Pin Assignment Pin Type, Pin Attribute
LEFT 9 Input, PULLUP
L2 10 Output, PULLUP
L8 16 Output, PULLUP
L6 17 Output, PULLUP
CLR 21 Input, PULLUP
RIGHT 22 Input, PULLUP
L7 25 Output, PULLUP
L0 28 Output, PULLUP
L5 30 Output, PULLUP
L3 31 Output, PULLUP
L1 32 Output, PULLUP
L4 43 Output, PULLUP
Design process management completed successfully
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