frmwrk.c

用UCOS系统实现的MIPS平台源码

/**************************************************************************
*                                                                         *
*   PROJECT     : TMON (Transparent monitor)                              *
*                                                                         *
*   MODULE      : FRMWRK.c                                                *
*                                                                         *
*   AUTHOR      : Michael Anburaj                                         *
*                 URL  : http://geocities.com/michaelanburaj/             *
*                 EMAIL: [e-mail]                       *
*                                                                         *
*   PROCESSOR   : MIPS 4Kc (32 bit RISC) - ATLAS board                    *
*                                                                         *
*   Tool-chain  : SDE & Cygnus                                            *
*                                                                         *
*   DESCRIPTION :                                                         *
*   This is the Framework module. Creates an operating infrastructure.    *
*                                                                         *
**************************************************************************/

#include "includes.h"
#include "frmwrk.h"
#include "consol.h"
#include "led.h"
#include <stdio.h>


#include "mips.h"
#include "atlas.h"


/* ********************************************************************* */
/* Global definitions */


/* ********************************************************************* */
/* File local definitions */

/* max. number of interrupt sources from interrupt controller */
#define MAX_IC_INTS		      32

/*
 * An 8-bit set is converted to a list of indices
 * by sequentially using and clearing the most significant bit number.
 */
static const U8 __abByte2MSBit[256] =
{
   0,
   0,
   1,1,
   2,2,2,2,
   3,3,3,3, 3,3,3,3,
   4,4,4,4, 4,4,4,4, 4,4,4,4, 4,4,4,4,

   5,5,5,5, 5,5,5,5, 5,5,5,5, 5,5,5,5,
   5,5,5,5, 5,5,5,5, 5,5,5,5, 5,5,5,5,

   6,6,6,6, 6,6,6,6, 6,6,6,6, 6,6,6,6,
   6,6,6,6, 6,6,6,6, 6,6,6,6, 6,6,6,6,
   6,6,6,6, 6,6,6,6, 6,6,6,6, 6,6,6,6,
   6,6,6,6, 6,6,6,6, 6,6,6,6, 6,6,6,6,

   7,7,7,7, 7,7,7,7, 7,7,7,7, 7,7,7,7,
   7,7,7,7, 7,7,7,7, 7,7,7,7, 7,7,7,7,
   7,7,7,7, 7,7,7,7, 7,7,7,7, 7,7,7,7,
   7,7,7,7, 7,7,7,7, 7,7,7,7, 7,7,7,7,
   7,7,7,7, 7,7,7,7, 7,7,7,7, 7,7,7,7,
   7,7,7,7, 7,7,7,7, 7,7,7,7, 7,7,7,7,
   7,7,7,7, 7,7,7,7, 7,7,7,7, 7,7,7,7,
   7,7,7,7, 7,7,7,7, 7,7,7,7, 7,7,7,7
};


/* ********************************************************************* */
/* Local functions */

/*
*********************************************************************************************
*                                       __vLogo
*
* Description: This routine display the Logo on the CONSOL port.
*
* Arguments  : none.
*
* Return     : none.
*
* Note(s)    : 
*********************************************************************************************
*/

void __vLogo(void)
{
	LED_vPuts(__mLEDLogo);

    CONSOL_Printf("\n\n%s Ver %s for %s :%s\n",__mLogo,__mVer,__mProcessor,__mDate);
    CONSOL_Printf("Built using %s on %s <%s>\n", "mipsisa32-elf-gcc",__DATE__,__TIME__);
    CONSOL_Printf("CONSOL: COM%d, %dbps, 8Bit, NP\n",__nConsolPort,__nConsolBaud);
	CONSOL_Printf("CPU Clk: %dMHz   MMU: %s   Cache: %s   Write Buf: %s\n",MCLK/1000000,
                       "ON","ON","ON");
    CONSOL_Printf("Developed by %s\n\n",__mAuthor);
}

/*
*********************************************************************************************
*                                       __vICHandler
*
* Description: This function implements the generic interrupt handler for the 
*              interrupt controller. It gets called by the First-level 
*              interrupt handler (C_INTHandler), when the HW-INT-line of 
*              the interrupt controller is asserted.
*
* Arguments  : none.
*
* Return     : none.
*
* Note(s)    : 
*********************************************************************************************
*/

static void __vICHandler(void)
{
    U32 pending, int_set;
    U32 h, j, index;
    char   msg[80];

    /* get the pending controller interrupts */

    while( (pending = REG32(KSEG1( ATLAS_ICTA_BASE + ICTA_INTSTATUS_OFS ))) != 0)
    {
        /* handle the max. int. sources in rounds of 8 */
        j = 0;

        while( j<MAX_IC_INTS )
        {
            /* select this round's max. 8 int. sources */
            int_set = (pending & 0x000000ff);

            /* check for any set */
            for (; int_set; int_set ^= 1 << (index & 7))
            {
                /*  Handle the interrupts in a sequence, 7..0 */
                index = __abByte2MSBit[int_set] + j;

				/* index == interrupt line */

                /*  Now, use the derived index to call into the
                 *  handler table.
		 		 */
		 		 
		 		((void(*)(void))(*(U32 *)(aICISR_SER+index*8)))();

		    
				/* Issue End Of Interrupt (EOI) */
				//arch_excep_eoi(index);
            }

            pending /= 256;
            j       += 8;
        }
    }
}

/*
*********************************************************************************************
*                                       __vTimer0ISR
*
* Description: This routine implements the FPGA Timer0 interrupt handler. It gets called by
*              the Second-level interrupt handler (__vICHandler)
*
* Arguments  : none.
*
* Return     : none.
*
* Note(s)    : 
*********************************************************************************************
*/

void __vTimer0ISR(void)
{
	rTMINTACK = 1;	
	OSTimeTick();
}



/* ********************************************************************* */
/* Global functions */

/*
*********************************************************************************************
*                                       C_INTHandler
*
* Description: This routine is the CPU interrupt exception handler (high-level part).
*
* Arguments  : none.
*
* Return     : pstC0 - Pointer to CP0 register structure.
*
* Note(s)    : 
*********************************************************************************************
*/

typedef struct CP0_tstREGS
{
	U32 wStatus;
	U32 wCause;
}CP0_tstREGS;

void C_INTHandler(CP0_tstREGS *pstC0)
{
    U32           h, index;
    U32		     int_pending;

    /*  Determine the pending interrupts based on CAUSE register IP field
     *  masked with STATUS register IM (Interrupt mask) field.
     */
    int_pending = REGFIELD( pstC0->wCause,  C0_CAUSE_IP ) &
		  REGFIELD( pstC0->wStatus, C0_STATUS_IM );

    /* validate 'int_pending' */
    if(int_pending <= (C0_CAUSE_IP_MSK >> C0_CAUSE_IP_SHF) )
    {
        /* Handle the 8 possible interrupts: 0..7 */

        /* do call handlers for all pending interrupts */
        for (; int_pending; int_pending ^= 1 << index)
        {
            /*  Handle the interrupts in a sequence, 7..0 */
            index = __abByte2MSBit[int_pending];

            /*  Now, use the derived index to call into the
             *  handler table (index = interrupt line).
             */

	    	((void(*)(void))(*(U32 *)(aCPUISR_SW0+index*8)))();
    	}
    }
}

/*
*********************************************************************************************
*                                       FRMWRK_vStartTicker
*
* Description: This routine starts FPGA Timer0 in timer mode for OS Tick.
*
* Arguments  : wTicksPerSec - Time ticks per second.
*
* Return     : none.
*
* Note(s)    : 
*********************************************************************************************
*/

void FRMWRK_vStartTicker(U32 wTicksPerSec)
{
#if OS_CRITICAL_METHOD == 3                      /* Allocate storage for CPU status register           */
    OS_CPU_SR  cpu_sr;
#endif

    OS_ENTER_CRITICAL();
       
    pICISR_TIM0 = (U32)__vTimer0ISR;

	rTM0CMP = (1000000/wTicksPerSec)-1;

        //enable timer interrupt by enabling the bit in the interrupt mask register
	REG32(KSEG1( ATLAS_ICTA_BASE + ICTA_INTSETEN_OFS )) = 1 << 1 /* ic_line */;

    OS_EXIT_CRITICAL();

}

/*
*********************************************************************************************
*                                       FRMWRK_vRamTest
*
* Description: This routine is used do RAM test.
*
* Arguments  : pbID   - Test identification string.
*              wSAddr - RAM starting address.
*              wEAddr - RAM end address.
*
* Return     : none.
*
* Note(s)    : Do not test the following areas using this routine:
*                       1. Stack
*                       2. Software vector table
*                       3. C Variables (RW & ZI)
*********************************************************************************************
*/

void FRMWRK_vRamTest(U8 *pbID,U32 wSAddr,U32 wEAddr)
{
        U32 wI,wJ;
        U8 bError=0;
        
        CONSOL_Printf("\n%s(%08xh-%08xh):WR",pbID,wSAddr,wEAddr);
        for(wI=wSAddr;wI<wEAddr;wI+=4)
        {
                *((volatile unsigned *)wI)=wI;
        }
        CONSOL_Printf("\b\bRD");
        for(wI=wSAddr;wI<wEAddr;wI+=4)
        {
                wJ=*((volatile unsigned *)wI);
                if(wJ!=wI)bError=1;
        }

        if(bError==0)CONSOL_Printf("\b\bO.K.\n");
        else CONSOL_Printf("\b\bFAIL\n");
}

/*
*********************************************************************************************
*                                       C_vMain
*
* Description: This is the main C entry function.
*
* Arguments  : none.
*
* Return     : none.
*
* Note(s)    : 
*********************************************************************************************
*/

void C_vMain(void)
{
	/* Register First-level (Low-level part, in assembly) CPU interrupt exception handler */
    pESR_INT = (U32)UCOS_INTHandler;

    /* Register Second-level interrupt handler */
    *((U32 *)(aCPUISR_SW0+ATLAS_CPU_ICTA*8)) = (U32)__vICHandler;
    CP0_vEnableIM(ATLAS_CPU_ICTA);

    CONSOL_Init(__nConsolBaud,__nConsolFifoEn);

    __vLogo();

    APP_vMain();

    CONSOL_Printf("APP has ended...\n");
}


/* ********************************************************************* */