atlas.h

用UCOS系统实现的MIPS平台源码

/* bit 14: ATXOKN */
#define ICTA_INTENABLE_ATXOKN_SHF	14
#define ICTA_INTENABLE_ATXOKN_MSK	(MSK(1) << ICTA_INTENABLE_ATXOKN_SHF)
#define ICTA_INTENABLE_ATXOKN_SET       ICTA_INTENABLE_ATXOKN_MSK

/* bit 13: DEG */
#define ICTA_INTENABLE_DEG_SHF	        13
#define ICTA_INTENABLE_DEG_MSK	        (MSK(1) << ICTA_INTENABLE_DEG_SHF)
#define ICTA_INTENABLE_DEG_SET	        ICTA_INTENABLE_DEG_MSK

/* bit 12: ENUM */
#define ICTA_INTENABLE_ENUM_SHF	        12
#define ICTA_INTENABLE_ENUM_MSK	        (MSK(1) << ICTA_INTENABLE_ENUM_SHF)
#define ICTA_INTENABLE_ENUM_SET	        ICTA_INTENABLE_ENUM_MSK

/* bit 11: PCID */
#define ICTA_INTENABLE_PCID_SHF	        11
#define ICTA_INTENABLE_PCID_MSK	        (MSK(1) << ICTA_INTENABLE_PCID_SHF)
#define ICTA_INTENABLE_PCID_SET	        ICTA_INTENABLE_PCID_MSK

/* bit 10: PCIC */
#define ICTA_INTENABLE_PCIC_SHF	        10
#define ICTA_INTENABLE_PCIC_MSK	        (MSK(1) << ICTA_INTENABLE_PCIC_SHF)
#define ICTA_INTENABLE_PCIC_SET	        ICTA_INTENABLE_PCIC_MSK

/* bit 9: PCIB */
#define ICTA_INTENABLE_PCIB_SHF	        9
#define ICTA_INTENABLE_PCIB_MSK	        (MSK(1) << ICTA_INTENABLE_PCIB_SHF)
#define ICTA_INTENABLE_PCIB_SET	        ICTA_INTENABLE_PCIB_MSK

/* bit 8: PCIA */
#define ICTA_INTENABLE_PCIA_SHF	        8
#define ICTA_INTENABLE_PCIA_MSK	        (MSK(1) << ICTA_INTENABLE_PCIA_SHF)
#define ICTA_INTENABLE_PCIA_SET	        ICTA_INTENABLE_PCIA_MSK

/* bit 7: NMI */
#define ICTA_INTENABLE_NMI_SHF	        7
#define ICTA_INTENABLE_NMI_MSK	        (MSK(1) << ICTA_INTENABLE_NMI_SHF)
#define ICTA_INTENABLE_NMI_SET	        ICTA_INTENABLE_NMI_MSK

/* bit 6: CORELO */
#define ICTA_INTENABLE_CORELO_SHF	6
#define ICTA_INTENABLE_CORELO_MSK	(MSK(1) << ICTA_INTENABLE_CORELO_SHF)
#define ICTA_INTENABLE_CORELO_SET	ICTA_INTENABLE_CORELO_MSK

/* bit 5: COREHI */
#define ICTA_INTENABLE_COREHI_SHF	5
#define ICTA_INTENABLE_COREHI_MSK	(MSK(1) << ICTA_INTENABLE_COREHI_SHF)
#define ICTA_INTENABLE_COREHI_SET	ICTA_INTENABLE_COREHI_MSK

/* bit 4: RTC */
#define ICTA_INTENABLE_RTC_SHF	        4
#define ICTA_INTENABLE_RTC_MSK	        (MSK(1) << ICTA_INTENABLE_RTC_SHF)
#define ICTA_INTENABLE_RTC_SET	        ICTA_INTENABLE_RTC_MSK

/* bit 2: TIM1 */
#define ICTA_INTENABLE_TIM1_SHF	        2
#define ICTA_INTENABLE_TIM1_MSK	        (MSK(1) << ICTA_INTENABLE_TIM1_SHF)
#define ICTA_INTENABLE_TIM1_SET	        ICTA_INTENABLE_TIM1_MSK

/* bit 1: TIM0 */
#define ICTA_INTENABLE_TIM0_SHF	        1
#define ICTA_INTENABLE_TIM0_MSK	        (MSK(1) << ICTA_INTENABLE_TIM0_SHF)
#define ICTA_INTENABLE_TIM0_SET	        ICTA_INTENABLE_TIM0_MSK

/* bit 0: SER */
#define ICTA_INTENABLE_SER_SHF	        0
#define ICTA_INTENABLE_SER_MSK	        (MSK(1) << ICTA_INTENABLE_SER_SHF)
#define ICTA_INTENABLE_SER_SET	        ICTA_INTENABLE_SER_MSK



/******** reg: INTSTATUS ********/
#define ICTA_INTSTATUS_OFS      0x20 /* value = INTRAW & INTENABLE      */

/* bit 19: PCISERRN */
#define ICTA_INTSTATUS_PCISERRN_SHF	19
#define ICTA_INTSTATUS_PCISERRN_MSK	(MSK(1) << ICTA_INTSTATUS_PCISERRN_SHF)
#define ICTA_INTSTATUS_PCISERRN_SET	ICTA_INTSTATUS_PCISERRN_MSK

/* bit 18: CONINTDN */
#define ICTA_INTSTATUS_CONINTDN_SHF	18
#define ICTA_INTSTATUS_CONINTDN_MSK	(MSK(1) << ICTA_INTSTATUS_CONINTDN_SHF)
#define ICTA_INTSTATUS_CONINTDN_SET	ICTA_INTSTATUS_CONINTDN_MSK

/* bit 17: CONINTCN */
#define ICTA_INTSTATUS_CONINTCN_SHF	17
#define ICTA_INTSTATUS_CONINTCN_MSK	(MSK(1) << ICTA_INTSTATUS_CONINTCN_SHF)
#define ICTA_INTSTATUS_CONINTCN_SET	ICTA_INTSTATUS_CONINTCN_MSK

/* bit 16: CONINTBN */
#define ICTA_INTSTATUS_CONINTBN_SHF	16
#define ICTA_INTSTATUS_CONINTBN_MSK	(MSK(1) << ICTA_INTSTATUS_CONINTBN_SHF)
#define ICTA_INTSTATUS_CONINTBN_SET	ICTA_INTSTATUS_CONINTBN_MSK

/* bit 15: CONINTAN */
#define ICTA_INTSTATUS_CONINTAN_SHF	15
#define ICTA_INTSTATUS_CONINTAN_MSK	(MSK(1) << ICTA_INTSTATUS_CONINTAN_SHF)
#define ICTA_INTSTATUS_CONINTAN_SET	ICTA_INTSTATUS_CONINTAN_MSK

/* bit 14: ATXOKN */
#define ICTA_INTSTATUS_ATXOKN_SHF	14
#define ICTA_INTSTATUS_ATXOKN_MSK	(MSK(1) << ICTA_INTSTATUS_ATXOKN_SHF)
#define ICTA_INTSTATUS_ATXOKN_SET	ICTA_INTSTATUS_ATXOKN_MSK

/* bit 13: DEG */
#define ICTA_INTSTATUS_DEG_SHF	        13
#define ICTA_INTSTATUS_DEG_MSK	        (MSK(1) << ICTA_INTSTATUS_DEG_SHF)
#define ICTA_INTSTATUS_DEG_SET	        ICTA_INTSTATUS_DEG_MSK

/* bit 12: ENUM */
#define ICTA_INTSTATUS_ENUM_SHF	        12
#define ICTA_INTSTATUS_ENUM_MSK	        (MSK(1) << ICTA_INTSTATUS_ENUM_SHF)
#define ICTA_INTSTATUS_ENUM_SET	        ICTA_INTSTATUS_ENUM_MSK

/* bit 11: PCID */
#define ICTA_INTSTATUS_PCID_SHF	        11
#define ICTA_INTSTATUS_PCID_MSK	        (MSK(1) << ICTA_INTSTATUS_PCID_SHF)
#define ICTA_INTSTATUS_PCID_SET	        ICTA_INTSTATUS_PCID_MSK

/* bit 10: PCIC */
#define ICTA_INTSTATUS_PCIC_SHF	        10
#define ICTA_INTSTATUS_PCIC_MSK	        (MSK(1) << ICTA_INTSTATUS_PCIC_SHF)
#define ICTA_INTSTATUS_PCIC_SET	        ICTA_INTSTATUS_PCIC_MSK

/* bit 9: PCIB */
#define ICTA_INTSTATUS_PCIB_SHF	        9
#define ICTA_INTSTATUS_PCIB_MSK	        (MSK(1) << ICTA_INTSTATUS_PCIB_SHF)
#define ICTA_INTSTATUS_PCIB_SET	        ICTA_INTSTATUS_PCIB_MSK

/* bit 8: PCIA */
#define ICTA_INTSTATUS_PCIA_SHF	        8
#define ICTA_INTSTATUS_PCIA_MSK	        (MSK(1) << ICTA_INTSTATUS_PCIA_SHF)
#define ICTA_INTSTATUS_PCIA_SET	        ICTA_INTSTATUS_PCIA_MSK

/* bit 7: NMI */
#define ICTA_INTSTATUS_NMI_SHF	        7
#define ICTA_INTSTATUS_NMI_MSK	        (MSK(1) << ICTA_INTSTATUS_NMI_SHF)
#define ICTA_INTSTATUS_NMI_SET	        ICTA_INTSTATUS_NMI_MSK

/* bit 6: CORELO */
#define ICTA_INTSTATUS_CORELO_SHF	6
#define ICTA_INTSTATUS_CORELO_MSK	(MSK(1) << ICTA_INTSTATUS_CORELO_SHF)
#define ICTA_INTSTATUS_CORELO_SET	ICTA_INTSTATUS_CORELO_MSK

/* bit 5: COREHI */
#define ICTA_INTSTATUS_COREHI_SHF	5
#define ICTA_INTSTATUS_COREHI_MSK	(MSK(1) << ICTA_INTSTATUS_COREHI_SHF)
#define ICTA_INTSTATUS_COREHI_SET	ICTA_INTSTATUS_COREHI_MSK

/* bit 4: RTC */
#define ICTA_INTSTATUS_RTC_SHF	        4
#define ICTA_INTSTATUS_RTC_MSK	        (MSK(1) << ICTA_INTSTATUS_RTC_SHF)
#define ICTA_INTSTATUS_RTC_SET	        ICTA_INTSTATUS_RTC_MSK

/* bit 2: TIM1 */
#define ICTA_INTSTATUS_TIM1_SHF	        2
#define ICTA_INTSTATUS_TIM1_MSK	        (MSK(1) << ICTA_INTSTATUS_TIM1_SHF)
#define ICTA_INTSTATUS_TIM1_SET	        ICTA_INTSTATUS_TIM1_MSK

/* bit 1: TIM0 */
#define ICTA_INTSTATUS_TIM0_SHF	        1
#define ICTA_INTSTATUS_TIM0_MSK	        (MSK(1) << ICTA_INTSTATUS_TIM0_SHF)
#define ICTA_INTSTATUS_TIM0_SET	        ICTA_INTSTATUS_TIM0_MSK

/* bit 0: SER */
#define ICTA_INTSTATUS_SER_SHF	        0
#define ICTA_INTSTATUS_SER_MSK	        (MSK(1) << ICTA_INTSTATUS_SER_SHF)
#define ICTA_INTSTATUS_SER_SET	        ICTA_INTSTATUS_SER_MSK



/************************************************************************
 *  C code I/O Register access definitions
*************************************************************************/

#ifndef _ASSEMBLER_

#include "sysdefs.h"

#ifdef __cplusplus
extern "C" {
#endif

/* Green LED */
#define rLEDGREEN       REG32(KSEG1(ATLAS_LEDGREEN))

/* LED BAR */
#define rLEDBAR         REG32(KSEG1(ATLAS_LEDBAR))

/* ASCII LEDs */
#define rASCIIWORD      REG32(KSEG1(ATLAS_ASCIIWORD))
#define rASCIIPOS0      REG32(KSEG1(ATLAS_ASCIIPOS0))
#define rASCIIPOS1      REG32(KSEG1(ATLAS_ASCIIPOS1))
#define rASCIIPOS2      REG32(KSEG1(ATLAS_ASCIIPOS2))
#define rASCIIPOS3      REG32(KSEG1(ATLAS_ASCIIPOS3))
#define rASCIIPOS4      REG32(KSEG1(ATLAS_ASCIIPOS4))
#define rASCIIPOS5      REG32(KSEG1(ATLAS_ASCIIPOS5))
#define rASCIIPOS6      REG32(KSEG1(ATLAS_ASCIIPOS6))
#define rASCIIPOS7      REG32(KSEG1(ATLAS_ASCIIPOS7))

/* Interrupt Controller Registers. BASE = 0x1F00.0000 */
#define rINTRAW         REG32(KSEG1(ATLAS_ICTA_BASE+0x00))
#define rINTSETEN       REG32(KSEG1(ATLAS_ICTA_BASE+0x08))
#define rINTRSTEN       REG32(KSEG1(ATLAS_ICTA_BASE+0x10))
#define rINTENABLE      REG32(KSEG1(ATLAS_ICTA_BASE+0x18))
#define rINTSTATUS      REG32(KSEG1(ATLAS_ICTA_BASE+0x20))

/* UART TI16C550 */
#define r16550RXTX      REG32(KSEG1(ATLAS_TI16C550_BASE+0x00))
#define r16550INTEN     REG32(KSEG1(ATLAS_TI16C550_BASE+0x08))
#define r16550IIFIFO    REG32(KSEG1(ATLAS_TI16C550_BASE+0x10))
#define r16550LCTRL     REG32(KSEG1(ATLAS_TI16C550_BASE+0x18))
#define r16550MCTRL     REG32(KSEG1(ATLAS_TI16C550_BASE+0x20))
#define r16550LSTAT     REG32(KSEG1(ATLAS_TI16C550_BASE+0x28))
#define r16550MSTAT     REG32(KSEG1(ATLAS_TI16C550_BASE+0x30))
#define r16550SCRATCH   REG32(KSEG1(ATLAS_TI16C550_BASE+0x38))
#define r16550DLL       REG32(KSEG1(ATLAS_TI16C550_BASE+0x00))
#define r16550DLM       REG32(KSEG1(ATLAS_TI16C550_BASE+0x08))

/* 24bit TIMER */
#define rTM0CNT         REG32(KSEG1(ATLAS_TMRA_BASE+0x00))
#define rTM0CMP         REG32(KSEG1(ATLAS_TMRA_BASE+0x08))
#define rTMINTACK       REG32(KSEG1(ATLAS_TMRA_BASE+0x20))

/* RTC */
#define rRTCADR         REG32(KSEG1(ATLAS_RTCADR))
#define rRTCDAT         REG32(KSEG1(ATLAS_RTCDAT))



/* Bit defintions */

/* r16550INTEN */
#define BIT_16550RXINT (1<<0)
#define BIT_16550TXINT (1<<1)
#define BIT_16550LSINT (1<<2)
#define BIT_16550MSINT (1<<3)

#ifdef __cplusplus
}
#endif

#endif /* _ASSEMBLER_ */



/************************************************************************
 *  Assembly & C code soft vectors definition
*************************************************************************/

/* Core Exception handler vectors */
#define _ESR_STARTADDRESS 0x00000500+KSEG0BASE

#define aESR_INT		(_ESR_STARTADDRESS+0x8*EX_INT)
#define aESR_MOD		(_ESR_STARTADDRESS+0x8*EX_MOD)
#define aESR_TLBL		(_ESR_STARTADDRESS+0x8*EX_TLBL)
#define aESR_TLBS		(_ESR_STARTADDRESS+0x8*EX_TLBS)
#define aESR_ADEL		(_ESR_STARTADDRESS+0x8*EX_ADEL)
#define aESR_ADES		(_ESR_STARTADDRESS+0x8*EX_ADES)
#define aESR_IBE		(_ESR_STARTADDRESS+0x8*EX_IBE)
#define aESR_DBE		(_ESR_STARTADDRESS+0x8*EX_DBE)
#define aESR_SYS		(_ESR_STARTADDRESS+0x8*EX_SYS)
#define aESR_BP			(_ESR_STARTADDRESS+0x8*EX_BP)
#define aESR_RI			(_ESR_STARTADDRESS+0x8*EX_RI)
#define aESR_CPU		(_ESR_STARTADDRESS+0x8*EX_CPU)
#define aESR_OV			(_ESR_STARTADDRESS+0x8*EX_OV)
#define aESR_TR			(_ESR_STARTADDRESS+0x8*EV_TR)
#define aESR_FPE		(_ESR_STARTADDRESS+0x8*EX_FPE)
#define aESR_WATCH		(_ESR_STARTADDRESS+0x8*EX_WATCH)
#define aESR_MCHECK		(_ESR_STARTADDRESS+0x8*EX_MCHECK)

/* CPU Interrupt handler vectors */
#define _CPUISR_STARTADDRESS _ESR_STARTADDRESS+0x100

#define aCPUISR_SW0		(_CPUISR_STARTADDRESS+0x00)
#define aCPUISR_SW1		(_CPUISR_STARTADDRESS+0x08)
#define aCPUISR_HW0		(_CPUISR_STARTADDRESS+0x10)
#define aCPUISR_HW1		(_CPUISR_STARTADDRESS+0x18)
#define aCPUISR_HW2		(_CPUISR_STARTADDRESS+0x20)
#define aCPUISR_HW3		(_CPUISR_STARTADDRESS+0x28)
#define aCPUISR_HW4		(_CPUISR_STARTADDRESS+0x30)
#define aCPUISR_HW5		(_CPUISR_STARTADDRESS+0x38)

/* Interrupt Controller Interrupt handler vectors */
#define _ICISR_STARTADDRESS aCPUISR_HW5+0x8

#define aICISR_SER		(_ICISR_STARTADDRESS+0x00)
#define aICISR_TIM0		(_ICISR_STARTADDRESS+0x08)
#define aICISR_TIM1		(_ICISR_STARTADDRESS+0x10)
/* bit 3: reserved */
#define aICISR_RTC		(_ICISR_STARTADDRESS+0x20)
#define aICISR_COREHI	(_ICISR_STARTADDRESS+0x28)
#define aICISR_CORELO	(_ICISR_STARTADDRESS+0x30)
#define aICISR_NMI		(_ICISR_STARTADDRESS+0x38)
#define aICISR_PCIA		(_ICISR_STARTADDRESS+0x40)
#define aICISR_PCIB		(_ICISR_STARTADDRESS+0x48)
#define aICISR_PCIC		(_ICISR_STARTADDRESS+0x50)
#define aICISR_PCID		(_ICISR_STARTADDRESS+0x68)
#define aICISR_ENUM		(_ICISR_STARTADDRESS+0x70)
#define aICISR_DEG		(_ICISR_STARTADDRESS+0x78)
#define aICISR_ATXOKN	(_ICISR_STARTADDRESS+0x80)
#define aICISR_CONINTAN	(_ICISR_STARTADDRESS+0x88)
#define aICISR_CONINTBN	(_ICISR_STARTADDRESS+0x90)
#define aICISR_CONINTCN	(_ICISR_STARTADDRESS+0x98)
#define aICISR_CONINTDN	(_ICISR_STARTADDRESS+0xa0)
#define aICISR_PCISERRN	(_ICISR_STARTADDRESS+0xa8)

/* Pointer definition for C code */
/* Core Exception handler vectors */
#define pESR_INT		(*(U32 *)aESR_INT)
#define pESR_MOD		(*(U32 *)aESR_MOD)
#define pESR_TLBL		(*(U32 *)aESR_TLBL)
#define pESR_TLBS		(*(U32 *)aESR_TLBS)
#define pESR_ADEL		(*(U32 *)aESR_ADEL)
#define pESR_ADES		(*(U32 *)aESR_ADES)
#define pESR_IBE		(*(U32 *)aESR_IBE)
#define pESR_DBE		(*(U32 *)aESR_DBE)
#define pESR_SYS		(*(U32 *)aESR_SYS)
#define pESR_BP			(*(U32 *)aESR_BP)
#define pESR_RI			(*(U32 *)aESR_RI)
#define pESR_CPU		(*(U32 *)aESR_CPU)
#define pESR_OV			(*(U32 *)aESR_OV)
#define pESR_TR			(*(U32 *)aESR_TR)
#define pESR_FPE		(*(U32 *)aESR_FPE)
#define pESR_WATCH		(*(U32 *)aESR_WATCH)
#define pESR_MCHECK		(*(U32 *)aESR_MCHECK)

/* CPU Interrupt handler vectors */
#define pCPUISR_SW0		(*(U32 *)aCPUISR_SW0)
#define pCPUISR_SW1		(*(U32 *)aCPUISR_SW1)
#define pCPUISR_HW0		(*(U32 *)aCPUISR_HW0)
#define pCPUISR_HW1		(*(U32 *)aCPUISR_HW1)
#define pCPUISR_HW2		(*(U32 *)aCPUISR_HW2)
#define pCPUISR_HW3		(*(U32 *)aCPUISR_HW3)
#define pCPUISR_HW4		(*(U32 *)aCPUISR_HW4)
#define pCPUISR_HW5		(*(U32 *)aCPUISR_HW5)

/* Interrupt Controller Interrupt handler vectors */
#define pICISR_SER		(*(U32 *)aICISR_SER)
#define pICISR_TIM0		(*(U32 *)aICISR_TIM0)
#define pICISR_TIM1		(*(U32 *)aICISR_TIM1)
/* bit 3: reserved */
#define pICISR_RTC		(*(U32 *)aICISR_RTC)
#define pICISR_COREHI	(*(U32 *)aICISR_COREHI)
#define pICISR_CORELO	(*(U32 *)aICISR_CORELO)
#define pICISR_NMI		(*(U32 *)aICISR_NMI)
#define pICISR_PCIA		(*(U32 *)aICISR_PCIA)
#define pICISR_PCIB		(*(U32 *)aICISR_PCIB)
#define pICISR_PCIC		(*(U32 *)aICISR_PCIC)
#define pICISR_PCID		(*(U32 *)aICISR_PCID)
#define pICISR_ENUM		(*(U32 *)aICISR_ENUM)
#define pICISR_DEG		(*(U32 *)aICISR_DEG)
#define pICISR_ATXOKN	(*(U32 *)aICISR_ATXOKN)
#define pICISR_CONINTAN	(*(U32 *)aICISR_CONINTAN)
#define pICISR_CONINTBN	(*(U32 *)aICISR_CONINTBN)
#define pICISR_CONINTCN	(*(U32 *)aICISR_CONINTCN)
#define pICISR_CONINTDN	(*(U32 *)aICISR_CONINTDN)
#define pICISR_PCISERRN	(*(U32 *)aICISR_PCISERRN)


/* ********************************************************************* */
/* Interface function definition */


/* ********************************************************************* */

#endif /* __ATLAS_H__ */