📄 atlas.h
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#define ATLAS_INTLINE_PCIB 16
#define ATLAS_INTLINE_PCIC 17
#define ATLAS_INTLINE_PCID 18
/* Compact PCI A..D */
#define ATLAS_INTLINE_CPCIA 8
#define ATLAS_INTLINE_CPCIB 9
#define ATLAS_INTLINE_CPCIC 10
#define ATLAS_INTLINE_CPCID 11
/* Local PCI devices */
#define ATLAS_INTLINE_9730 ATLAS_INTLINE_PCIB
#define ATLAS_INTLINE_SCSI ATLAS_INTLINE_PCIC
/* Other devices */
#define ATLAS_INTLINE_COREHI 5
/**** CPU interrupt lines used by devices ****/
#define ATLAS_CPU_ICTA C0_STATUS_IM_HW0
/* MISC definitions */
/* Lowest possible frequency for cpu (used during init for conservative
* setup of timing (e.g. SDRAM refresh)
*/
#define ATLAS_CPUFREQ_LOWEST_MHZ 2
/* PCI device numbers */
#define ATLAS_DEVNUM_SAA9730 PCI_IDSEL2DEVNUM(ATLAS_IDSEL_SAA9730)
#define ATLAS_DEVNUM_PCI_SLOT PCI_IDSEL2DEVNUM(ATLAS_IDSEL_CONNECTOR)
/************************************************************************
* Interrupt Controller definition
*************************************************************************/
/**** Number of interrupt lines ****/
#define ICTA_IC_COUNT 20
/* Relative Register Addresses & bit fields */
/******** reg: INTRAW ********/
#define ICTA_INTRAW_OFS 0x00 /* RAW value on external int lines */
/* bit 19: PCISERRN */
#define ICTA_INTRAW_PCISERRN_SHF 19
#define ICTA_INTRAW_PCISERRN_MSK (MSK(1) << ICTA_INTRAW_PCISERRN_SHF)
#define ICTA_INTRAW_PCISERRN_SET ICTA_INTRAW_PCISERRN_MSK
/* bit 18: CONINTDN */
#define ICTA_INTRAW_CONINTDN_SHF 18
#define ICTA_INTRAW_CONINTDN_MSK (MSK(1) << ICTA_INTRAW_CONINTDN_SHF)
#define ICTA_INTRAW_CONINTDN_SET ICTA_INTRAW_CONINTDN_MSK
/* bit 17: CONINTCN */
#define ICTA_INTRAW_CONINTCN_SHF 17
#define ICTA_INTRAW_CONINTCN_MSK (MSK(1) << ICTA_INTRAW_CONINTCN_SHF)
#define ICTA_INTRAW_CONINTCN_SET ICTA_INTRAW_CONINTCN_MSK
/* bit 16: CONINTBN */
#define ICTA_INTRAW_CONINTBN_SHF 16
#define ICTA_INTRAW_CONINTBN_MSK (MSK(1) << ICTA_INTRAW_CONINTBN_SHF)
#define ICTA_INTRAW_CONINTBN_SET ICTA_INTRAW_CONINTBN_MSK
/* bit 15: CONINTAN */
#define ICTA_INTRAW_CONINTAN_SHF 15
#define ICTA_INTRAW_CONINTAN_MSK (MSK(1) << ICTA_INTRAW_CONINTAN_SHF)
#define ICTA_INTRAW_CONINTAN_SET ICTA_INTRAW_CONINTAN_MSK
/* bit 14: ATXOKN */
#define ICTA_INTRAW_ATXOKN_SHF 14
#define ICTA_INTRAW_ATXOKN_MSK (MSK(1) << ICTA_INTRAW_ATXOKN_SHF)
#define ICTA_INTRAW_ATXOKN_SET ICTA_INTRAW_ATXOKN_MSK
/* bit 13: DEG */
#define ICTA_INTRAW_DEG_SHF 13
#define ICTA_INTRAW_DEG_MSK (MSK(1) << ICTA_INTRAW_DEG_SHF)
#define ICTA_INTRAW_DEG_SET ICTA_INTRAW_DEG_MSK
/* bit 12: ENUM */
#define ICTA_INTRAW_ENUM_SHF 12
#define ICTA_INTRAW_ENUM_MSK (MSK(1) << ICTA_INTRAW_ENUM_SHF)
#define ICTA_INTRAW_ENUM_SET ICTA_INTRAW_ENUM_MSK
/* bit 11: PCID */
#define ICTA_INTRAW_PCID_SHF 11
#define ICTA_INTRAW_PCID_MSK (MSK(1) << ICTA_INTRAW_PCID_SHF)
#define ICTA_INTRAW_PCID_SET ICTA_INTRAW_PCID_MSK
/* bit 10: PCIC */
#define ICTA_INTRAW_PCIC_SHF 10
#define ICTA_INTRAW_PCIC_MSK (MSK(1) << ICTA_INTRAW_PCIC_SHF)
#define ICTA_INTRAW_PCIC_SET ICTA_INTRAW_PCIC_MSK
/* bit 9: PCIB */
#define ICTA_INTRAW_PCIB_SHF 9
#define ICTA_INTRAW_PCIB_MSK (MSK(1) << ICTA_INTRAW_PCIB_SHF)
#define ICTA_INTRAW_PCIB_SET ICTA_INTRAW_PCIB_MSK
/* bit 8: PCIA */
#define ICTA_INTRAW_PCIA_SHF 8
#define ICTA_INTRAW_PCIA_MSK (MSK(1) << ICTA_INTRAW_PCIA_SHF)
#define ICTA_INTRAW_PCIA_SET ICTA_INTRAW_PCIA_MSK
/* bit 7: NMI */
#define ICTA_INTRAW_NMI_SHF 7
#define ICTA_INTRAW_NMI_MSK (MSK(1) << ICTA_INTRAW_NMI_SHF)
#define ICTA_INTRAW_NMI_SET ICTA_INTRAW_NMI_MSK
/* bit 6: CORELO */
#define ICTA_INTRAW_CORELO_SHF 6
#define ICTA_INTRAW_CORELO_MSK (MSK(1) << ICTA_INTRAW_CORELO_SHF)
#define ICTA_INTRAW_CORELO_SET ICTA_INTRAW_CORELO_MSK
/* bit 5: COREHI */
#define ICTA_INTRAW_COREHI_SHF 5
#define ICTA_INTRAW_COREHI_MSK (MSK(1) << ICTA_INTRAW_COREHI_SHF)
#define ICTA_INTRAW_COREHI_SET ICTA_INTRAW_COREHI_MSK
/* bit 4: RTC */
#define ICTA_INTRAW_RTC_SHF 4
#define ICTA_INTRAW_RTC_MSK (MSK(1) << ICTA_INTRAW_RTC_SHF)
#define ICTA_INTRAW_RTC_SET ICTA_INTRAW_RTC_MSK
/* bit 2: TIM1 */
#define ICTA_INTRAW_TIM1_SHF 2
#define ICTA_INTRAW_TIM1_MSK (MSK(1) << ICTA_INTRAW_TIM1_SHF)
#define ICTA_INTRAW_TIM1_SET ICTA_INTRAW_TIM1_MSK
/* bit 1: TIM0 */
#define ICTA_INTRAW_TIM0_SHF 1
#define ICTA_INTRAW_TIM0_MSK (MSK(1) << ICTA_INTRAW_TIM0_SHF)
#define ICTA_INTRAW_TIM0_SET ICTA_INTRAW_TIM0_MSK
/* bit 0: SER */
#define ICTA_INTRAW_SER_SHF 0
#define ICTA_INTRAW_SER_MSK (MSK(1) << ICTA_INTRAW_SER_SHF)
#define ICTA_INTRAW_SER_SET ICTA_INTRAW_SER_MSK
/******** reg: INTSETEN ********/
#define ICTA_INTSETEN_OFS 0x08 /* SET enable int ("1") per bit */
/* bit 19: PCISERRN */
#define ICTA_INTSETEN_PCISERRN_SHF 19
#define ICTA_INTSETEN_PCISERRN_MSK (MSK(1) << ICTA_INTSETEN_PCISERRN_SHF)
#define ICTA_INTSETEN_PCISERRN_SET ICTA_INTSETEN_PCISERRN_MSK
/* bit 18: CONINTDN */
#define ICTA_INTSETEN_CONINTDN_SHF 18
#define ICTA_INTSETEN_CONINTDN_MSK (MSK(1) << ICTA_INTSETEN_CONINTDN_SHF)
#define ICTA_INTSETEN_CONINTDN_SET ICTA_INTSETEN_CONINTDN_MSK
/* bit 17: CONINTCN */
#define ICTA_INTSETEN_CONINTCN_SHF 17
#define ICTA_INTSETEN_CONINTCN_MSK (MSK(1) << ICTA_INTSETEN_CONINTCN_SHF)
#define ICTA_INTSETEN_CONINTCN_SET ICTA_INTSETEN_CONINTCN_MSK
/* bit 16: CONINTBN */
#define ICTA_INTSETEN_CONINTBN_SHF 16
#define ICTA_INTSETEN_CONINTBN_MSK (MSK(1) << ICTA_INTSETEN_CONINTBN_SHF)
#define ICTA_INTSETEN_CONINTBN_SET ICTA_INTSETEN_CONINTBN_MSK
/* bit 15: CONINTAN */
#define ICTA_INTSETEN_CONINTAN_SHF 15
#define ICTA_INTSETEN_CONINTAN_MSK (MSK(1) << ICTA_INTSETEN_CONINTAN_SHF)
#define ICTA_INTSETEN_CONINTAN_SET ICTA_INTSETEN_CONINTAN_MSK
/* bit 14: ATXOKN */
#define ICTA_INTSETEN_ATXOKN_SHF 14
#define ICTA_INTSETEN_ATXOKN_MSK (MSK(1) << ICTA_INTSETEN_ATXOKN_SHF)
#define ICTA_INTSETEN_ATXOKN_SET ICTA_INTSETEN_ATXOKN_MSK
/* bit 13: DEG */
#define ICTA_INTSETEN_DEG_SHF 13
#define ICTA_INTSETEN_DEG_MSK (MSK(1) << ICTA_INTSETEN_DEG_SHF)
#define ICTA_INTSETEN_DEG_SET ICTA_INTSETEN_DEG_MSK
/* bit 12: ENUM */
#define ICTA_INTSETEN_ENUM_SHF 12
#define ICTA_INTSETEN_ENUM_MSK (MSK(1) << ICTA_INTSETEN_ENUM_SHF)
#define ICTA_INTSETEN_ENUM_SET ICTA_INTSETEN_ENUM_MSK
/* bit 11: PCID */
#define ICTA_INTSETEN_PCID_SHF 11
#define ICTA_INTSETEN_PCID_MSK (MSK(1) << ICTA_INTSETEN_PCID_SHF)
#define ICTA_INTSETEN_PCID_SET ICTA_INTSETEN_PCID_MSK
/* bit 10: PCIC */
#define ICTA_INTSETEN_PCIC_SHF 10
#define ICTA_INTSETEN_PCIC_MSK (MSK(1) << ICTA_INTSETEN_PCIC_SHF)
#define ICTA_INTSETEN_PCIC_SET ICTA_INTSETEN_PCIC_MSK
/* bit 9: PCIB */
#define ICTA_INTSETEN_PCIB_SHF 9
#define ICTA_INTSETEN_PCIB_MSK (MSK(1) << ICTA_INTSETEN_PCIB_SHF)
#define ICTA_INTSETEN_PCIB_SET ICTA_INTSETEN_PCIB_MSK
/* bit 8: PCIA */
#define ICTA_INTSETEN_PCIA_SHF 8
#define ICTA_INTSETEN_PCIA_MSK (MSK(1) << ICTA_INTSETEN_PCIA_SHF)
#define ICTA_INTSETEN_PCIA_SET ICTA_INTSETEN_PCIA_MSK
/* bit 7: NMI */
#define ICTA_INTSETEN_NMI_SHF 7
#define ICTA_INTSETEN_NMI_MSK (MSK(1) << ICTA_INTSETEN_NMI_SHF)
#define ICTA_INTSETEN_NMI_SET ICTA_INTSETEN_NMI_MSK
/* bit 6: CORELO */
#define ICTA_INTSETEN_CORELO_SHF 6
#define ICTA_INTSETEN_CORELO_MSK (MSK(1) << ICTA_INTSETEN_CORELO_SHF)
#define ICTA_INTSETEN_CORELO_SET ICTA_INTSETEN_CORELO_MSK
/* bit 5: COREHI */
#define ICTA_INTSETEN_COREHI_SHF 5
#define ICTA_INTSETEN_COREHI_MSK (MSK(1) << ICTA_INTSETEN_COREHI_SHF)
#define ICTA_INTSETEN_COREHI_SET ICTA_INTSETEN_COREHI_MSK
/* bit 4: RTC */
#define ICTA_INTSETEN_RTC_SHF 4
#define ICTA_INTSETEN_RTC_MSK (MSK(1) << ICTA_INTSETEN_RTC_SHF)
#define ICTA_INTSETEN_RTC_SET ICTA_INTSETEN_RTC_MSK
/* bit 2: TIM1 */
#define ICTA_INTSETEN_TIM1_SHF 2
#define ICTA_INTSETEN_TIM1_MSK (MSK(1) << ICTA_INTSETEN_TIM1_SHF)
#define ICTA_INTSETEN_TIM1_SET ICTA_INTSETEN_TIM1_MSK
/* bit 1: TIM0 */
#define ICTA_INTSETEN_TIM0_SHF 1
#define ICTA_INTSETEN_TIM0_MSK (MSK(1) << ICTA_INTSETEN_TIM0_SHF)
#define ICTA_INTSETEN_TIM0_SET ICTA_INTSETEN_TIM0_MSK
/* bit 0: SER */
#define ICTA_INTSETEN_SER_SHF 0
#define ICTA_INTSETEN_SER_MSK (MSK(1) << ICTA_INTSETEN_SER_SHF)
#define ICTA_INTSETEN_SER_SET ICTA_INTSETEN_SER_MSK
/******** reg: INTRSTEN ********/
#define ICTA_INTRSTEN_OFS 0x10 /* RESET enable int ("1") per bit */
/* bit 19: PCISERRN */
#define ICTA_INTRSTEN_PCISERRN_SHF 19
#define ICTA_INTRSTEN_PCISERRN_MSK (MSK(1) << ICTA_INTRSTEN_PCISERRN_SHF)
#define ICTA_INTRSTEN_PCISERRN_SET ICTA_INTRSTEN_PCISERRN_MSK
/* bit 18: CONINTDN */
#define ICTA_INTRSTEN_CONINTDN_SHF 18
#define ICTA_INTRSTEN_CONINTDN_MSK (MSK(1) << ICTA_INTRSTEN_CONINTDN_SHF)
#define ICTA_INTRSTEN_CONINTDN_SET ICTA_INTRSTEN_CONINTDN_MSK
/* bit 17: CONINTCN */
#define ICTA_INTRSTEN_CONINTCN_SHF 17
#define ICTA_INTRSTEN_CONINTCN_MSK (MSK(1) << ICTA_INTRSTEN_CONINTCN_SHF)
#define ICTA_INTRSTEN_CONINTCN_SET ICTA_INTRSTEN_CONINTCN_MSK
/* bit 16: CONINTBN */
#define ICTA_INTRSTEN_CONINTBN_SHF 16
#define ICTA_INTRSTEN_CONINTBN_MSK (MSK(1) << ICTA_INTRSTEN_CONINTBN_SHF)
#define ICTA_INTRSTEN_CONINTBN_SET ICTA_INTRSTEN_CONINTBN_MSK
/* bit 15: CONINTAN */
#define ICTA_INTRSTEN_CONINTAN_SHF 15
#define ICTA_INTRSTEN_CONINTAN_MSK (MSK(1) << ICTA_INTRSTEN_CONINTAN_SHF)
#define ICTA_INTRSTEN_CONINTAN_SET ICTA_INTRSTEN_CONINTAN_MSK
/* bit 14: ATXOKN */
#define ICTA_INTRSTEN_ATXOKN_SHF 14
#define ICTA_INTRSTEN_ATXOKN_MSK (MSK(1) << ICTA_INTRSTEN_ATXOKN_SHF)
#define ICTA_INTRSTEN_ATXOKN_SET ICTA_INTRSTEN_ATXOKN_MSK
/* bit 13: DEG */
#define ICTA_INTRSTEN_DEG_SHF 13
#define ICTA_INTRSTEN_DEG_MSK (MSK(1) << ICTA_INTRSTEN_DEG_SHF)
#define ICTA_INTRSTEN_DEG_SET ICTA_INTRSTEN_DEG_MSK
/* bit 12: ENUM */
#define ICTA_INTRSTEN_ENUM_SHF 12
#define ICTA_INTRSTEN_ENUM_MSK (MSK(1) << ICTA_INTRSTEN_ENUM_SHF)
#define ICTA_INTRSTEN_ENUM_SET ICTA_INTRSTEN_ENUM_MSK
/* bit 11: PCID */
#define ICTA_INTRSTEN_PCID_SHF 11
#define ICTA_INTRSTEN_PCID_MSK (MSK(1) << ICTA_INTRSTEN_PCID_SHF)
#define ICTA_INTRSTEN_PCID_SET ICTA_INTRSTEN_PCID_MSK
/* bit 10: PCIC */
#define ICTA_INTRSTEN_PCIC_SHF 10
#define ICTA_INTRSTEN_PCIC_MSK (MSK(1) << ICTA_INTRSTEN_PCIC_SHF)
#define ICTA_INTRSTEN_PCIC_SET ICTA_INTRSTEN_PCIC_MSK
/* bit 9: PCIB */
#define ICTA_INTRSTEN_PCIB_SHF 9
#define ICTA_INTRSTEN_PCIB_MSK (MSK(1) << ICTA_INTRSTEN_PCIB_SHF)
#define ICTA_INTRSTEN_PCIB_SET ICTA_INTRSTEN_PCIB_MSK
/* bit 8: PCIA */
#define ICTA_INTRSTEN_PCIA_SHF 8
#define ICTA_INTRSTEN_PCIA_MSK (MSK(1) << ICTA_INTRSTEN_PCIA_SHF)
#define ICTA_INTRSTEN_PCIA_SET ICTA_INTRSTEN_PCIA_MSK
/* bit 7: NMI */
#define ICTA_INTRSTEN_NMI_SHF 7
#define ICTA_INTRSTEN_NMI_MSK (MSK(1) << ICTA_INTRSTEN_NMI_SHF)
#define ICTA_INTRSTEN_NMI_SET ICTA_INTRSTEN_NMI_MSK
/* bit 6: CORELO */
#define ICTA_INTRSTEN_CORELO_SHF 6
#define ICTA_INTRSTEN_CORELO_MSK (MSK(1) << ICTA_INTRSTEN_CORELO_SHF)
#define ICTA_INTRSTEN_CORELO_SET ICTA_INTRSTEN_CORELO_MSK
/* bit 5: COREHI */
#define ICTA_INTRSTEN_COREHI_SHF 5
#define ICTA_INTRSTEN_COREHI_MSK (MSK(1) << ICTA_INTRSTEN_COREHI_SHF)
#define ICTA_INTRSTEN_COREHI_SET ICTA_INTRSTEN_COREHI_MSK
/* bit 4: RTC */
#define ICTA_INTRSTEN_RTC_SHF 4
#define ICTA_INTRSTEN_RTC_MSK (MSK(1) << ICTA_INTRSTEN_RTC_SHF)
#define ICTA_INTRSTEN_RTC_SET ICTA_INTRSTEN_RTC_MSK
/* bit 2: TIM1 */
#define ICTA_INTRSTEN_TIM1_SHF 2
#define ICTA_INTRSTEN_TIM1_MSK (MSK(1) << ICTA_INTRSTEN_TIM1_SHF)
#define ICTA_INTRSTEN_TIM1_SET ICTA_INTRSTEN_TIM1_MSK
/* bit 1: TIM0 */
#define ICTA_INTRSTEN_TIM0_SHF 1
#define ICTA_INTRSTEN_TIM0_MSK (MSK(1) << ICTA_INTRSTEN_TIM0_SHF)
#define ICTA_INTRSTEN_TIM0_SET ICTA_INTRSTEN_TIM0_MSK
/* bit 0: SER */
#define ICTA_INTRSTEN_SER_SHF 0
#define ICTA_INTRSTEN_SER_MSK (MSK(1) << ICTA_INTRSTEN_SER_SHF)
#define ICTA_INTRSTEN_SER_SET ICTA_INTRSTEN_SER_MSK
/******** reg: INTENABLE ********/
#define ICTA_INTENABLE_OFS 0x18 /* INT enable mask status */
/* bit 19: PCISERRN */
#define ICTA_INTENABLE_PCISERRN_SHF 19
#define ICTA_INTENABLE_PCISERRN_MSK (MSK(1) << ICTA_INTENABLE_PCISERRN_SHF)
#define ICTA_INTENABLE_PCISERRN_SET ICTA_INTENABLE_PCISERRN_MSK
/* bit 18: CONINTDN */
#define ICTA_INTENABLE_CONINTDN_SHF 18
#define ICTA_INTENABLE_CONINTDN_MSK (MSK(1) << ICTA_INTENABLE_CONINTDN_SHF)
#define ICTA_INTENABLE_CONINTDN_SET ICTA_INTENABLE_CONINTDN_MSK
/* bit 17: CONINTCN */
#define ICTA_INTENABLE_CONINTCN_SHF 17
#define ICTA_INTENABLE_CONINTCN_MSK (MSK(1) << ICTA_INTENABLE_CONINTCN_SHF)
#define ICTA_INTENABLE_CONINTCN_SET ICTA_INTENABLE_CONINTCN_MSK
/* bit 16: CONINTBN */
#define ICTA_INTENABLE_CONINTBN_SHF 16
#define ICTA_INTENABLE_CONINTBN_MSK (MSK(1) << ICTA_INTENABLE_CONINTBN_SHF)
#define ICTA_INTENABLE_CONINTBN_SET ICTA_INTENABLE_CONINTBN_MSK
/* bit 15: CONINTAN */
#define ICTA_INTENABLE_CONINTAN_SHF 15
#define ICTA_INTENABLE_CONINTAN_MSK (MSK(1) << ICTA_INTENABLE_CONINTAN_SHF)
#define ICTA_INTENABLE_CONINTAN_SET ICTA_INTENABLE_CONINTAN_MSK
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