pwm.c

lm3s下lwip的udp

    HWREG(ulBase + PWM_O_ISC) = PWM_ISC_INTFAULT0;
}

//*****************************************************************************
//
//! Gets the interrupt status for a PWM module.
//!
//! \param ulBase is the base address of the PWM module.
//! \param bMasked specifies whether masked or raw interrupt status is
//! returned.
//!
//! If \e bMasked is set as \b true, then the masked interrupt status is
//! returned; otherwise, the raw interrupt status will be returned.
//!
//! \return The current interrupt status, enumerated as a bit field of
//! \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, \b PWM_INT_GEN_3,
//! \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, \b PWM_INT_FAULT2, and
//! \b PWM_INT_FAULT3.
//!
//*****************************************************************************
unsigned long
PWMIntStatus(unsigned long ulBase, tBoolean bMasked)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == PWM_BASE);

    //
    // Read and return either the module's raw or enabled interrupt status.
    //
    if(bMasked == true)
    {
        return(HWREG(ulBase + PWM_O_ISC));
    }
    else
    {
        return(HWREG(ulBase + PWM_O_RIS));
    }
}

//*****************************************************************************
//
//! Clears the fault interrupt for a PWM module.
//!
//! \param ulBase is the base address of the PWM module.
//! \param ulFaultInts specifies the fault interrupts to clear.
//!
//! Clears one or more fault interrupts by writing to the appropriate bit of
//! the PWM interrupt status register.  The parameter \e ulFaultInts must be
//! the logical OR of any of \b PWM_INT_FAULT0, \b PWM_INT_FAULT1,
//! \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3.
//!
//! When running on a device supporting extended PWM fault handling, the fault
//! interrupts are derived by performing a logical OR of each of the configured
//! fault trigger signals for a given generator.  Therefore, these interrupts
//! are not directly related to the four possible FAULTn inputs to the device
//! but indicate that a fault has been signalled to one of the four possible
//! PWM generators.  On a device without extended PWM fault handling, the
//! interrupt is directly related to the state of the single FAULT pin.
//!
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
//! several cycles before the interrupt source is actually cleared.  Therefore,
//! it is recommended that the interrupt source be cleared early in the
//! interrupt handler (as opposed to the very last action) to avoid returning
//! from the interrupt handler before the interrupt source is actually cleared.
//! Failure to do so may result in the interrupt handler being immediately
//! reentered (since NVIC still sees the interrupt source asserted).
//!
//! \return None.
//
//*****************************************************************************
void
PWMFaultIntClearExt(unsigned long ulBase, unsigned long ulFaultInts)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == PWM_BASE);
    ASSERT((ulFaultInts & ~(PWM_INT_FAULT0 | PWM_INT_FAULT1 |
                            PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0);

    //
    // Clear the supplied fault bits.
    //
    HWREG(ulBase + PWM_O_ISC) = ulFaultInts;
}

//*****************************************************************************
//
//! Configures the minimum fault period and fault pin senses for a given
//! PWM generator.
//!
//! \param ulBase is the base address of the PWM module.
//! \param ulGen is the PWM generator whose fault configuration is being set.
//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
//! \param ulMinFaultPeriod is the minimum fault active period expressed in
//! PWM clock cycles.
//! \param ulFaultSenses indicates which sense of each FAULT input should be
//! considered the ``asserted'' state.  Valid values are logical OR
//! combinations of \b PWM_FAULTn_SENSE_HIGH and \b PWM_FAULTn_SENSE_LOW.
//!
//! This function sets the minimum fault period for a given generator along
//! with the sense of each of the 4 possible fault inputs.  The minimum fault
//! period is expressed in PWM clock cycles and takes effect only if
//! PWMGenConfigure() is called with flag \b PWM_GEN_MODE_FAULT_PER set in the
//! \e ulConfig parameter.  When a fault input is asserted, the minimum fault
//! period timer ensures that it remains asserted for at least the number of
//! clock cycles specified.
//!
//! \note This function is only available on devices supporting extended PWM
//! fault handling.
//!
//! \return None.
//
//*****************************************************************************
void
PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen,
                     unsigned long ulMinFaultPeriod,
                     unsigned long ulFaultSenses)
{
    //
    // Check the arguments.
    //
    ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
    ASSERT(ulBase == PWM_BASE);
    ASSERT(PWMGenValid(ulGen));
    ASSERT(ulMinFaultPeriod < PWM_X_MINFLTPER_M);
    ASSERT((ulFaultSenses & ~(PWM_FAULT0_SENSE_HIGH | PWM_FAULT0_SENSE_LOW |
                              PWM_FAULT1_SENSE_HIGH | PWM_FAULT1_SENSE_LOW |
                              PWM_FAULT2_SENSE_HIGH | PWM_FAULT2_SENSE_LOW |
                              PWM_FAULT3_SENSE_HIGH | PWM_FAULT3_SENSE_LOW)) ==
           0);

    //
    // Write the minimum fault period.
    //
    HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_MINFLTPER) = ulMinFaultPeriod;

    //
    // Write the fault senses.
    //
    HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSEN) = ulFaultSenses;
}

//*****************************************************************************
//
//! Configures the set of fault triggers for a given PWM generator.
//!
//! \param ulBase is the base address of the PWM module.
//! \param ulGen is the PWM generator whose fault triggers are being set.  Must
//! be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
//! \param ulGroup indicates the subset of possible faults that are to be
//! configured.  This must be \b PWM_FAULT_GROUP_0.
//! \param ulFaultTriggers defines the set of inputs that are to contribute
//! towards generation of the fault signal to the given PWM generator.  For
//! \b PWM_FAULT_GROUP_0, this will be the logical OR of \b PWM_FAULT_FAULT0,
//! \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or \b PWM_FAULT_FAULT3.
//!
//! This function allows selection of the set of fault inputs that will be
//! combined to generate a fault condition to a given PWM generator.  By
//! default, all generators use only FAULT0 (for backwards compatibility) but
//! if PWMGenConfigure() is called with flag \b PWM_GEN_MODE_FAULT_SRC in the
//! \e ulConfig parameter, extended fault handling is enabled and this function
//! must be called to configure the fault triggers.
//!
//! The fault signal to the PWM generator is generated by ORing together each
//! of the signals whose inputs are specified in the \e ulFaultTriggers
//! parameter after having adjusted the sense of each FAULTn input based on the
//! configuration previously set using a call to PWMGenFaultConfigure().
//!
//! \note This function is only available on devices supporting extended PWM
//! fault handling.
//!
//! \return None.
//
//*****************************************************************************
void
PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen,
                      unsigned long ulGroup, unsigned long ulFaultTriggers)
{
    //
    // Check for valid parameters.
    //
    ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
    ASSERT(ulBase == PWM_BASE);
    ASSERT(PWMGenValid(ulGen));
    ASSERT(ulGroup == PWM_FAULT_GROUP_0);
    ASSERT((ulFaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 |
                                PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == 0);

    //
    // Write the fault triggers to the appropriate register.
    //
    HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC0) = ulFaultTriggers;
}

//*****************************************************************************
//
//! Returns the set of fault triggers currently configured for a given PWM
//! generator.
//!
//! \param ulBase is the base address of the PWM module.
//! \param ulGen is the PWM generator whose fault triggers are being queried.
//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
//! \param ulGroup indicates the subset of faults that are being queried.  This
//! must be \b PWM_FAULT_GROUP_0.
//!
//! This function allows an application to query the current set of inputs that
//! contribute towards the generation of a fault condition to a given PWM
//! generator.
//!
//! \note This function is only available on devices supporting extended PWM
//! fault handling.
//!
//! \return Returns the current fault triggers configured for the fault group
//! provided.  For \b PWM_FAULT_GROUP_0, the returned value will be a logical
//! OR of \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or
//! \b PWM_FAULT_FAULT3.
//
//*****************************************************************************
unsigned long
PWMGenFaultTriggerGet(unsigned long ulBase, unsigned long ulGen,
                      unsigned long ulGroup)
{
    //
    // Check for valid parameters.
    //
    ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
    ASSERT(ulBase == PWM_BASE);
    ASSERT(PWMGenValid(ulGen));
    ASSERT(ulGroup == PWM_FAULT_GROUP_0);

    //
    // Return the current fault triggers.
    //
    return(HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC0));
}

//*****************************************************************************
//
//! Returns the current state of the fault triggers for a given PWM generator.
//!
//! \param ulBase is the base address of the PWM module.
//! \param ulGen is the PWM generator whose fault trigger states are being
//! queried.  Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or
//! \b PWM_GEN_3.
//! \param ulGroup indicates the subset of faults that are being queried.  This
//! must be \b PWM_FAULT_GROUP_0.
//!
//! This function allows an application to query the current state of each of
//! the fault trigger inputs to a given PWM generator.  The current state of
//! each fault trigger input is returned unless PWMGenConfigure() has
//! previously been called with flag \b PWM_GEN_MODE_LATCH_FAULT in the
//! \e ulConfig parameter in which case the returned status is the latched
//! fault trigger status.
//!
//! If latched faults are configured, the application must call
//! PWMGenFaultClear() to clear each trigger.
//!
//! \note This function is only available on devices supporting extended PWM
//! fault handling.
//!
//! \return Returns the current state of the fault triggers for the given PWM
//! generator.  A set bit indicates that the associated trigger is active.  For
//! \b PWM_FAULT_GROUP_0, the returned value will be a logical OR of
//! \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or
//! \b PWM_FAULT_FAULT3.
//
//*****************************************************************************
unsigned long
PWMGenFaultStatus(unsigned long ulBase, unsigned long ulGen,
                  unsigned long ulGroup)
{
    //
    // Check for valid parameters.
    //
    ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
    ASSERT(ulBase == PWM_BASE);
    ASSERT(PWMGenValid(ulGen));
    ASSERT(ulGroup == PWM_FAULT_GROUP_0);

    //
    // Return the current fault status.
    //
    return(HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT0));
}

//*****************************************************************************
//
//! Clears one or more latched fault triggers for a given PWM generator.
//!
//! \param ulBase is the base address of the PWM module.
//! \param ulGen is the PWM generator whose fault trigger states are being
//! queried.  Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or
//! \b PWM_GEN_3.
//! \param ulGroup indicates the subset of faults that are being queried.  This
//! must be \b PWM_FAULT_GROUP_0.
//! \param ulFaultTriggers is the set of fault triggers which are to be
//! cleared.
//!
//! This function allows an application to clear the fault triggers for a given
//! PWM generator.  This is only required if PWMGenConfigure() has previously
//! been called with flag \b PWM_GEN_MODE_LATCH_FAULT in parameter \e ulConfig.
//!
//! \note This function is only available on devices supporting extended PWM
//! fault handling.
//!
//! \return None.
//
//*****************************************************************************
void
PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen,
                 unsigned long ulGroup, unsigned long ulFaultTriggers)
{
    //
    // Check for valid parameters.
    //
    ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
    ASSERT(ulBase == PWM_BASE);
    ASSERT(PWMGenValid(ulGen));
    ASSERT(ulGroup == PWM_FAULT_GROUP_0);
    ASSERT((ulFaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 |
                                PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == 0);

    //
    // Clear the given faults.
    //
    HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT0) =
        ulFaultTriggers;
}

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************