📄 hal_intr.h
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asm volatile ( \ "ldr r4,=10f;" \ "bx r4;" \ ".code 32;" \ "10:;" \ "mrs %0,cpsr;" \ "mrs r4,cpsr;" \ "orr r4,r4,#0xC0;" \ "msr cpsr,r4;" \ "ldr r4,=10f+1;" \ "bx r4;" \ ".code 16;" \ "10:;" \ : "=r"(_old_) \ : \ : "r4" \ );
#define HAL_ENABLE_INTERRUPTS() \ asm volatile ( \ "ldr r3,=10f;" \ "bx r3;" \ ".code 32;" \ "10:;" \ "mrs r3,cpsr;" \ "bic r3,r3,#0xC0;" \ "msr cpsr,r3;" \ "ldr r3,=10f+1;" \ "bx r3;" \ ".code 16;" \ "10:;" \ : \ : \ : "r3" \ );
#define HAL_RESTORE_INTERRUPTS(_old_) \ asm volatile ( \ "ldr r3,=10f;" \ "bx r3;" \ ".code 32;" \ "10:;" \ "mrs r3,cpsr;" \ "and r4,%0,#0xC0;" \ "bic r3,r3,#0xC0;" \ "orr r3,r3,r4;" \ "msr cpsr,r3;" \ "ldr r3,=10f+1;" \ "bx r3;" \ ".code 16;" \ "10:;" \ : \ : "r"(_old_) \ : "r3", "r4" \ );
#define HAL_QUERY_INTERRUPTS(_old_) \ asm volatile ( \ "ldr r4,=10f;" \ "bx r4;" \ ".code 32;" \ "10:;" \ "mrs r4,cpsr;" \ "and r4,r4,#0xC0;" \ "eor %0,r4,#0xC0;" \ "ldr r4,=10f+1;" \ "bx r4;" \ ".code 16;" \ "10:;" \ : "=r"(_old_) \ : \ : "r4" \ );
#else
externC cyg_uint32 hal_disable_interrupts(void);
externC void hal_enable_interrupts(void);
externC void hal_restore_interrupts(cyg_uint32);
externC cyg_uint32 hal_query_interrupts(void);
#define HAL_DISABLE_INTERRUPTS(_old_) \ _old_ = hal_disable_interrupts();
#define HAL_ENABLE_INTERRUPTS() \ hal_enable_interrupts();
#define HAL_RESTORE_INTERRUPTS(_old_) \ hal_restore_interrupts(_old_);
#define HAL_QUERY_INTERRUPTS(_old_) \ _old_ = hal_query_interrupts();
#endif
#endif // __thumb__
//--------------------------------------------------------------------------
// Routine to execute DSRs using separate interrupt stack
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
externC void hal_interrupt_stack_call_pending_DSRs(void);
#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \ hal_interrupt_stack_call_pending_DSRs()
// these are offered solely for stack usage testing
// if they are not defined, then there is no interrupt stack.
#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
#define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack
// use them to declare these extern however you want:
// extern char HAL_INTERRUPT_STACK_BASE[];
// extern char HAL_INTERRUPT_STACK_TOP[];
// is recommended
#endif
//--------------------------------------------------------------------------
// Vector translation.
#ifndef HAL_TRANSLATE_VECTOR
#define HAL_TRANSLATE_VECTOR(_vector_,_index_) \ (_index_) = (_vector_)
#endif
//--------------------------------------------------------------------------
// Interrupt and VSR attachment macros
#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \ CYG_MACRO_START \ cyg_uint32 _index_; \ HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ \ if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \ (_state_) = 0; \ else \ (_state_) = 1; \ CYG_MACRO_END
#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \ CYG_MACRO_START \ if( hal_interrupt_handlers[_vector_] == (CYG_ADDRESS)hal_default_isr ) \ { \ hal_interrupt_handlers[_vector_] = (CYG_ADDRESS)_isr_; \ hal_interrupt_data[_vector_] = (CYG_ADDRWORD) _data_; \ hal_interrupt_objects[_vector_] = (CYG_ADDRESS)_object_; \ } \ CYG_MACRO_END
#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \ CYG_MACRO_START \ if( hal_interrupt_handlers[_vector_] == (CYG_ADDRESS)_isr_ ) \ { \ hal_interrupt_handlers[_vector_] = (CYG_ADDRESS)hal_default_isr; \ hal_interrupt_data[_vector_] = 0; \ hal_interrupt_objects[_vector_] = 0; \ } \ CYG_MACRO_END
#define HAL_VSR_GET( _vector_, _pvsr_ ) \ *(CYG_ADDRESS *)(_pvsr_) = hal_vsr_table[_vector_];
#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) \ CYG_MACRO_START \ if( _poldvsr_ != NULL ) \ *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \ hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \ CYG_MACRO_END
//--------------------------------------------------------------------------
// Interrupt controller access
externC void hal_interrupt_mask(int);
externC void hal_interrupt_unmask(int);
externC void hal_interrupt_acknowledge(int);
externC void hal_interrupt_configure(int, int, int);
externC void hal_interrupt_set_level(int, int);
#define HAL_INTERRUPT_MASK( _vector_ ) \ hal_interrupt_mask( _vector_ )
#define HAL_INTERRUPT_UNMASK( _vector_ ) \ hal_interrupt_unmask( _vector_ )
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \ hal_interrupt_acknowledge( _vector_ )
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \ hal_interrupt_configure( _vector_, _level_, _up_ )
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \ hal_interrupt_set_level( _vector_, _level_ )
//--------------------------------------------------------------------------
// Clock control
externC void hal_clock_initialize(cyg_uint32);
externC void hal_clock_read(cyg_uint32 *);
externC void hal_clock_reset(cyg_uint32, cyg_uint32);
#define HAL_CLOCK_INITIALIZE( _period_ ) hal_clock_initialize( _period_ )
#define HAL_CLOCK_RESET( _vec_, _period_ ) hal_clock_reset( _vec_, _period_ )
#define HAL_CLOCK_READ( _pvalue_ ) hal_clock_read( _pvalue_ )
#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
# ifndef HAL_CLOCK_LATENCY
# define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ( (cyg_uint32 *)_pvalue_ )
# endif
#endif
//--------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_INTR_H
// End of hal_intr.h
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