📄 cpu.h
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#ifdef __ASSEMBLER__
# define ARM_CACHE_COPROCESSOR_NUM p15
# define ARM_COPROCESSOR_OPCODE_DONT_CARE 0x0
# define ARM_COPROCESSOR_RM_DONT_CARE c0
#else /* __ASSEMBLER__ */
# define ARM_CACHE_COPROCESSOR_NUM "p15"
# define ARM_COPROCESSOR_OPCODE_DONT_CARE "0x0"
# define ARM_COPROCESSOR_RM_DONT_CARE "c0"
#endif /* __ASSEMBLER__ */
#ifdef __ASSEMBLER__
# define ARM_ID_REGISTER c0
# define ARM_CONTROL_REGISTER c1
# define ARM_TRANSLATION_TABLE_BASE_REGISTER c2
# define ARM_DOMAIN_ACCESS_CONTROL_REGISTER c3
# define ARM_FAULT_STATUS_REGISTER c5
# define ARM_FAULT_ADDRESS_REGISTER c6
# define ARM_CACHE_OPERATIONS_REGISTER c7
# define ARM_TLB_OPERATIONS_REGISTER c8
# define ARM_READ_BUFFER_OPERATIONS_REGISTER c9
#else /* __ASSEMBLER__ */
# define ARM_ID_REGISTER "c0"
# define ARM_CONTROL_REGISTER "c1"
# define ARM_TRANSLATION_TABLE_BASE_REGISTER "c2"
# define ARM_DOMAIN_ACCESS_CONTROL_REGISTER "c3"
# define ARM_FAULT_STATUS_REGISTER "c5"
# define ARM_FAULT_ADDRESS_REGISTER "c6"
# define ARM_CACHE_OPERATIONS_REGISTER "c7"
# define ARM_TLB_OPERATIONS_REGISTER "c8"
# define ARM_READ_BUFFER_OPERATIONS_REGISTER "c9"
#endif /* __ASSEMBLER__ */
/*
* SA-1100 Cache and MMU ID Register value
*/
#define ARM_ID_MASK 0xFFFFFFF0
#define ARM_ID_VALUE 0x4401a110
/*
* SA-1100 Cache Control Register Bit Fields and Masks
*/
#define ARM_MMU_DISABLED 0x00000000
#define ARM_MMU_ENABLED 0x00000001
#define ARM_MMU_MASK 0x00000001
#define ARM_ADDRESS_FAULT_DISABLED 0x00000000
#define ARM_ADDRESS_FAULT_ENABLED 0x00000002
#define ARM_ADDRESS_FAULT_MASK 0x00000002
#define ARM_DATA_CACHE_DISABLED 0x00000000
#define ARM_DATA_CACHE_ENABLED 0x00000004
#define ARM_DATA_CACHE_MASK 0x00000004
#define ARM_WRITE_BUFFER_DISABLED 0x00000000
#define ARM_WRITE_BUFFER_ENABLED 0x00000008
#define ARM_WRITE_BUFFER_MASK 0x00000008
#define ARM_LITTLE_ENDIAN 0x00000000
#define ARM_BIG_ENDIAN 0x00000080
#define ARM_ACCESS_CHECKS_NONE 0x00000000
#define ARM_ACCESS_CHECKS_SYSTEM 0x00000100
#define ARM_ACCESS_CHECKS_ROM 0x00000200
#define ARM_INSTRUCTION_CACHE_DISABLED 0x00000000
#define ARM_INSTRUCTION_CACHE_ENABLED 0x00001000
#define ARM_INSTRUCTION_CACHE_MASK 0x00001000
#define ARM_VIRTUAL_IVR_BASE_00000000 0x00000000
#define ARM_VIRTUAL_IVR_BASE_FFFF0000 0x00002000
#define ARM_CONTROL_SBZ_MASK 0x00001FFF
/*
* SA-1100 Translation Table Base Bit Masks
*/
#define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000
/*
* SA-1100 Domain Access Control Bit Masks
*/
#define ARM_DOMAIN_0_MASK 0x00000003
#define ARM_DOMAIN_1_MASK 0x0000000C
#define ARM_DOMAIN_2_MASK 0x00000030
#define ARM_DOMAIN_3_MASK 0x000000C0
#define ARM_DOMAIN_4_MASK 0x00000300
#define ARM_DOMAIN_5_MASK 0x00000C00
#define ARM_DOMAIN_6_MASK 0x00003000
#define ARM_DOMAIN_7_MASK 0x0000C000
#define ARM_DOMAIN_8_MASK 0x00030000
#define ARM_DOMAIN_9_MASK 0x000C0000
#define ARM_DOMAIN_10_MASK 0x00300000
#define ARM_DOMAIN_11_MASK 0x00C00000
#define ARM_DOMAIN_12_MASK 0x03000000
#define ARM_DOMAIN_13_MASK 0x0C000000
#define ARM_DOMAIN_14_MASK 0x30000000
#define ARM_DOMAIN_15_MASK 0xC0000000
#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num))
#define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num))
#define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num))
/*
* SA-1100 Fault Status Bit Masks
*/
#define ARM_FAULT_STATUS_MASK 0x0000000F
#define ARM_DOMAIN_MASK 0x000000F0
#define ARM_DATA_BREAKPOINT_MASK 0x00000200
/*
* SA-1100 Cache Control Operations Definitions
*/
#ifdef __ASSEMBLER__
# define ARM_FLUSH_CACHE_INST_DATA_OPCODE 0x0
# define ARM_FLUSH_CACHE_INST_DATA_RM c7
# define ARM_FLUSH_CACHE_INST_OPCODE 0x0
# define ARM_FLUSH_CACHE_INST_RM c5
# define ARM_FLUSH_CACHE_DATA_OPCODE 0x0
# define ARM_FLUSH_CACHE_DATA_RM c6
# define ARM_FLUSH_CACHE_DATA_SINGLE_OPCODE 0x1
# define ARM_FLUSH_CACHE_DATA_SINGLE_RM c6
# define ARM_CLEAN_CACHE_DATA_ENTRY_OPCODE 0x1
# define ARM_CLEAN_CACHE_DATA_ENTRY_RM c10
# define ARM_DRAIN_CACHE_WRITE_BUFFER_OPCODE 0x4
# define ARM_DRAIN_CACHE_WRITE_BUFFER_RM c10
#else /* __ASSEMBLER__ */
# define ARM_FLUSH_CACHE_INST_DATA_OPCODE "0x0"
# define ARM_FLUSH_CACHE_INST_DATA_RM "c7"
# define ARM_FLUSH_CACHE_INST_OPCODE "0x0"
# define ARM_FLUSH_CACHE_INST_RM "c5"
# define ARM_FLUSH_CACHE_DATA_OPCODE "0x0"
# define ARM_FLUSH_CACHE_DATA_RM "c6"
# define ARM_FLUSH_CACHE_DATA_SINGLE_OPCODE "0x1"
# define ARM_FLUSH_CACHE_DATA_SINGLE_RM "c6"
# define ARM_CLEAN_CACHE_DATA_ENTRY_OPCODE "0x1"
# define ARM_CLEAN_CACHE_DATA_ENTRY_RM "c10"
# define ARM_DRAIN_CACHE_WRITE_BUFFER_OPCODE "0x4"
# define ARM_DRAIN_CACHE_WRITE_BUFFER_RM "c10"
#endif /* __ASSEMBLER__ */
/*
* SA-1100 TLB Operations Definitions
*/
#ifdef __ASSEMBLER__
# define ARM_FLUSH_INST_DATA_TLB_OPCODE 0x0
# define ARM_FLUSH_INST_DATA_TLB_RM c7
# define ARM_FLUSH_INST_TLB_OPCODE 0x0
# define ARM_FLUSH_INST_TLB_RM c5
# define ARM_FLUSH_DATA_TLB_OPCODE 0x0
# define ARM_FLUSH_DATA_TLB_RM c6
# define ARM_FLUSH_DATA_ENTRY_TLB_OPCODE 0x1
# define ARM_FLUSH_DATA_ENTRY_TLB_RM c6
#else /* __ASSEMBLER__ */
# define ARM_FLUSH_INST_DATA_TLB_OPCODE "0x0"
# define ARM_FLUSH_INST_DATA_TLB_RM "c7"
# define ARM_FLUSH_INST_TLB_OPCODE "0x0"
# define ARM_FLUSH_INST_TLB_RM "c5"
# define ARM_FLUSH_DATA_TLB_OPCODE "0x0"
# define ARM_FLUSH_DATA_TLB_RM "c6"
# define ARM_FLUSH_DATA_ENTRY_TLB_OPCODE "0x1"
# define ARM_FLUSH_DATA_ENTRY_TLB_RM "c6"
#endif /* __ASSEMBLER__ */
/*
* SA-1100 Read-Buffer Operations Definitions
*/
#ifdef __ASSEMBLER__
# define ARM_FLUSH_ALL_BUFFERS_OPCODE 0x0
# define ARM_FLUSH_ALL_BUFFERS_RM c0
# define ARM_FLUSH_BUFFER_0_OPCODE 0x1
# define ARM_FLUSH_BUFFER_0_RM c0
# define ARM_FLUSH_BUFFER_1_OPCODE 0x1
# define ARM_FLUSH_BUFFER_1_RM c1
# define ARM_FLUSH_BUFFER_2_OPCODE 0x1
# define ARM_FLUSH_BUFFER_2_RM c2
# define ARM_FLUSH_BUFFER_3_OPCODE 0x1
# define ARM_FLUSH_BUFFER_3_RM c3
# define ARM_LOAD_BUFFER_0_1_WORD_OPCODE 0x2
# define ARM_LOAD_BUFFER_0_1_WORD_RM c0
# define ARM_LOAD_BUFFER_0_4_WORD_OPCODE 0x2
# define ARM_LOAD_BUFFER_0_4_WORD_RM c4
# define ARM_LOAD_BUFFER_0_8_WORD_OPCODE 0x2
# define ARM_LOAD_BUFFER_0_8_WORD_RM c8
# define ARM_LOAD_BUFFER_1_1_WORD_OPCODE 0x2
# define ARM_LOAD_BUFFER_1_1_WORD_RM c1
# define ARM_LOAD_BUFFER_1_4_WORD_OPCODE 0x2
# define ARM_LOAD_BUFFER_1_4_WORD_RM c5
# define ARM_LOAD_BUFFER_1_8_WORD_OPCODE 0x2
# define ARM_LOAD_BUFFER_1_8_WORD_RM c9
# define ARM_LOAD_BUFFER_2_1_WORD_OPCODE 0x2
# define ARM_LOAD_BUFFER_2_1_WORD_RM c2
# define ARM_LOAD_BUFFER_2_4_WORD_OPCODE 0x2
# define ARM_LOAD_BUFFER_2_4_WORD_RM c6
# define ARM_LOAD_BUFFER_2_8_WORD_OPCODE 0x2
# define ARM_LOAD_BUFFER_2_8_WORD_RM cA
# define ARM_LOAD_BUFFER_3_1_WORD_OPCODE 0x2
# define ARM_LOAD_BUFFER_3_1_WORD_RM c3
# define ARM_LOAD_BUFFER_3_4_WORD_OPCODE 0x2
# define ARM_LOAD_BUFFER_3_4_WORD_RM c7
# define ARM_LOAD_BUFFER_3_8_WORD_OPCODE 0x2
# define ARM_LOAD_BUFFER_3_8_WORD_RM cB
# define ARM_DISABLE_USER_MCR_ACCESS_OPCODE 0x4
# define ARM_DISABLE_USER_MCR_ACCESS_RM c0
# define ARM_ENABLE_USER_MCR_ACCESS_OPCODE 0x5
# define ARM_ENABLE_USER_MCR_ACCESS_RM c0
#else /* __ASSEMBLER__ */
# define ARM_FLUSH_ALL_BUFFERS_OPCODE "0x0"
# define ARM_FLUSH_ALL_BUFFERS_RM "c0"
# define ARM_FLUSH_BUFFER_0_OPCODE "0x1"
# define ARM_FLUSH_BUFFER_0_RM "c0"
# define ARM_FLUSH_BUFFER_1_OPCODE "0x1"
# define ARM_FLUSH_BUFFER_1_RM "c1"
# define ARM_FLUSH_BUFFER_2_OPCODE "0x1"
# define ARM_FLUSH_BUFFER_2_RM "c2"
# define ARM_FLUSH_BUFFER_3_OPCODE "0x1"
# define ARM_FLUSH_BUFFER_3_RM "c3"
# define ARM_LOAD_BUFFER_0_1_WORD_OPCODE "0x2"
# define ARM_LOAD_BUFFER_0_1_WORD_RM "c0"
# define ARM_LOAD_BUFFER_0_4_WORD_OPCODE "0x2"
# define ARM_LOAD_BUFFER_0_4_WORD_RM "c4"
# define ARM_LOAD_BUFFER_0_8_WORD_OPCODE "0x2"
# define ARM_LOAD_BUFFER_0_8_WORD_RM "c8"
# define ARM_LOAD_BUFFER_1_1_WORD_OPCODE "0x2"
# define ARM_LOAD_BUFFER_1_1_WORD_RM "c1"
# define ARM_LOAD_BUFFER_1_4_WORD_OPCODE "0x2"
# define ARM_LOAD_BUFFER_1_4_WORD_RM "c5"
# define ARM_LOAD_BUFFER_1_8_WORD_OPCODE "0x2"
# define ARM_LOAD_BUFFER_1_8_WORD_RM "c9"
# define ARM_LOAD_BUFFER_2_1_WORD_OPCODE "0x2"
# define ARM_LOAD_BUFFER_2_1_WORD_RM "c2"
# define ARM_LOAD_BUFFER_2_4_WORD_OPCODE "0x2"
# define ARM_LOAD_BUFFER_2_4_WORD_RM "c6"
# define ARM_LOAD_BUFFER_2_8_WORD_OPCODE "0x2"
# define ARM_LOAD_BUFFER_2_8_WORD_RM "cA"
# define ARM_LOAD_BUFFER_3_1_WORD_OPCODE "0x2"
# define ARM_LOAD_BUFFER_3_1_WORD_RM "c3"
# define ARM_LOAD_BUFFER_3_4_WORD_OPCODE "0x2"
# define ARM_LOAD_BUFFER_3_4_WORD_RM "c7"
# define ARM_LOAD_BUFFER_3_8_WORD_OPCODE "0x2"
# define ARM_LOAD_BUFFER_3_8_WORD_RM "cB"
# define ARM_DISABLE_USER_MCR_ACCESS_OPCODE "0x4"
# define ARM_DISABLE_USER_MCR_ACCESS_RM "c0"
# define ARM_ENABLE_USER_MCR_ACCESS_OPCODE "0x5"
# define ARM_ENABLE_USER_MCR_ACCESS_RM "c0"
#endif /* __ASSEMBLER__ */
/*
* ARM(R) First Level Descriptor Format Definitions
*/
#ifndef __ASSEMBLER__
struct ARM_MMU_FIRST_LEVEL_FAULT {
int id : 2;
int sbz : 30;
};
#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
int id : 2;
int imp : 2;
int domain : 4;
int sbz : 1;
int base_address : 23;
};
#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
struct ARM_MMU_FIRST_LEVEL_SECTION {
int id : 2;
int b : 1;
int c : 1;
int imp : 1;
int domain : 4;
int sbz0 : 1;
int ap : 2;
int sbz1 : 8;
int base_address : 12;
};
#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
struct ARM_MMU_FIRST_LEVEL_RESERVED {
int id : 2;
int sbz : 30;
};
#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \ (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, cacheable, bufferable, perm) \ { \ register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \ \ desc.word = 0; \ desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \ desc.section.domain = 0; \ desc.section.c = (cacheable); \ desc.section.b = (bufferable); \ desc.section.ap = (perm); \ desc.section.base_address = (actual_base); \ *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) = desc.word; \ }
union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
unsigned long word;
struct ARM_MMU_FIRST_LEVEL_FAULT fault;
struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
struct ARM_MMU_FIRST_LEVEL_SECTION section;
struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
};
#endif /* __ASSEMBLER__ */
#define ARM_UNCACHEABLE 0
#define ARM_CACHEABLE 1
#define ARM_UNBUFFERABLE 0
#define ARM_BUFFERABLE 1
#define ARM_ACCESS_PERM_NONE_NONE 0
#define ARM_ACCESS_PERM_RO_NONE 0
#define ARM_ACCESS_PERM_RO_RO 0
#define ARM_ACCESS_PERM_RW_NONE 1
#define ARM_ACCESS_PERM_RW_RO 2
#define ARM_ACCESS_PERM_RW_RW 3
#define ARM_SECTION_SIZE SZ_1M
#define ARM_SMALL_PAGE_SIZE SZ_4K
#define ARM_LARGE_PAGE_SIZE SZ_64K
#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE SZ_16K
#define ARM_SECOND_LEVEL_PAGE_TABLE_SIZE SZ_1K
#endif /* MMU */
#endif // __ARM_CPU_H__
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