vectors.s

eCos/RedBoot for勤研ARM AnywhereII(4510) 含全部源代码

//========================================================================
//
//    vectors.S
//
//    ARM exception vectors
//
//========================================================================
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    Sonys <[e-mail]>
// Contributors: 
// Date:         2004-06-17
// Purpose:      
// Description:  
//
// Copyright (C) 2004 DevBone Software 
// All rights reserved.
//####DESCRIPTIONEND####
//==========================================================================
#define VECTOR_ENTRY 0x0c000000        

#define CPSR_IRQ_DISABLE	0x80	// IRQ disabled when =1
#define CPSR_FIQ_DISABLE	0x40	// FIQ disabled when =1
#define CPSR_THUMB_ENABLE	0x20	// Thumb mode when =1
#define CPSR_USER_MODE		0x10
#define CPSR_FIQ_MODE		0x11
#define CPSR_IRQ_MODE		0x12
#define CPSR_SUPERVISOR_MODE	0x13
#define CPSR_UNDEF_MODE		0x1B

#define CPSR_MODE_BITS          0x1F

#define CPSR_INITIAL (CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
#define CPSR_THREAD_INITIAL (CPSR_SUPERVISOR_MODE)

#define PTR(name)               \
.##name: .word  name

# define UNMAPPED(x) (x)
                                
#define UNMAPPED_PTR(name)              \
.##name: .word  UNMAPPED(name)

//==========================================================================
// Hardware exception vectors.
//   This entire section will be copied to location 0x0000 at startup time.
//
        .code   32
        .section ".vectors","ax"
                        
        .global __exception_handlers
__exception_handlers:
        b       reset_vector                    // 0x00
        ldr     pc,.undefined_instruction       // 0x04
        ldr     pc,.software_interrupt          // 0x08 start && software int
        ldr     pc,.abort_prefetch              // 0x0C
        ldr     pc,.abort_data                  // 0x10
        .word   0                               // unused
        ldr     pc,.IRQ                         // 0x18
        ldr     pc,.FIQ                         // 0x1C

        .global vectors
vectors:
UNMAPPED_PTR(reset_vector)                      // 0x20
PTR(undefined_instruction)                      // 0x24
PTR(software_interrupt)                         // 0x28
PTR(abort_prefetch)                             // 0x2C
PTR(abort_data)                                 // 0x30
        .word   0                               // 0x34
PTR(IRQ)                                        // 0x38
PTR(FIQ)                                        // 0x3c
        .global reset_vector
        .type   reset_vector,function
reset_vector:
warm_reset:
// =========================================================================
// Real startup code. We jump here from the reset vector to set up the world.
        .globl  start
start:  

        // Reset software interrupt pointer
	ldr     r0,=VECTOR_ENTRY
	ldr     r1,.__exception_handlers
        ldr     r2,[r1,#0x08]   // software interrupt
        str     r2,[r0,#0x08]
        ldr     r2,[r1,#0x28]   // software interrupt
        str     r2,[r0,#0x28]
        ldr     r2,[r1,#0x18]   // IRQ
        str     r2,[r0,#0x18]
        ldr     r2,[r1,#0x38]
        str     r2,[r0,#0x38]
        ldr     r2,[r1,#0x1C]   // FIQ
        str     r2,[r0,#0x1C]
        ldr     r2,[r1,#0x3C]
        str     r2,[r0,#0x3C]
        ldr     r2,[r1,#0x0C]   // abort (prefetch)
        str     r2,[r0,#0x0C]
        ldr     r2,[r1,#0x2C]   
        str     r2,[r0,#0x2C]
        ldr     r2,[r1,#0x10]   // abort (data)
        str     r2,[r0,#0x10]
        ldr     r2,[r1,#0x30]
        str     r2,[r0,#0x30]

#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
        // Set up reset vector
	ldr     r0,=VECTOR_ENTRY
        ldr     r1,.__exception_handlers
        ldr     r2,[r1,#0x00]    // reset vector intstruction
        str     r2,[r0,#0x00]
        ldr     r2,=warm_reset
        str     r2,[r0,#0x20]
        // Relocate [copy] data from ROM to RAM
        ldr     r3,.__rom_data_start
        ldr     r4,.__ram_data_start
        ldr     r5,.__ram_data_end
        cmp     r4,r5           // jump if no data to move
        beq     2f
        sub     r3,r3,#4        // loop adjustments
        sub     r4,r4,#4
1:      ldr     r0,[r3,#4]!     // copy info
        str     r0,[r4,#4]!
        cmp     r4,r5
        bne     1b
2:
#endif

        // initialize interrupt/exception environments
        ldr     sp,.__startup_stack
        mov     r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_IRQ_MODE)
        msr     cpsr,r0
        ldr     sp,.__exception_stack
        mov     r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_UNDEF_MODE)
        msr     cpsr,r0
        ldr     sp,.__exception_stack

        // initialize CPSR (machine state register)
        mov     r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
        msr     cpsr,r0

        // Note: some functions in LIBGCC1 will cause a "restore from SPSR"!!
        msr     spsr,r0

        // initialize stack
        ldr     sp,.__startup_stack

        // clear BSS
        ldr     r1,.__bss_start
        ldr     r2,.__bss_end
        mov     r0,#0
        cmp     r1,r2
        beq     2f
1:      str     r0,[r1],#4
        cmp     r1,r2
        bls     1b
2:

        bl      main

_start_hang:
        b       _start_hang

        .code   32
        
        .global reset_platform
        .type   reset_platform,function
reset_platform:         
        mov     r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
        msr     cpsr,r0
        b       warm_reset

        .code   32
undefined_instruction:
	sub   r0,lr,#4                // PC at time of interrupt (ARM)
	movs pc, lr

        .code   32
software_interrupt:
	sub   r0,lr,#4                // PC at time of interrupt (ARM)
	movs pc, lr

        .code   32
abort_prefetch:
	sub   r0,lr,#4                // PC at time of interrupt (ARM)
	movs pc, lr

        .code   32
abort_data:
	sub   r0,lr,#4                // PC at time of interrupt (ARM)
	movs pc, lr

        .code   32
FIQ:
        // We can get here from any non-user mode.
	sub   r0,lr,#4                // PC at time of interrupt (ARM)
	b	.
	movs pc, lr

IRQ:
        // Note: I use this exception stack while saving the context because
        // the current SP does not seem to be always valid in this CPU mode.
	sub   r0,lr,#4                // PC at time of interrupt (ARM)
	b	.
	movs pc, lr

// Dummy/support functions

        .global __gccmain
        .global _psr
        .global _sp

__gccmain:
        mov     pc,lr   

_psr:
        mrs     r0,cpsr
        mov     pc,lr

_sp:
        mov     r0,sp
        mov     pc,lr

//
// Pointers to various objects.
//
PTR(__startup_stack)
PTR(__exception_stack)
PTR(__bss_start)
PTR(__bss_end)
PTR(_end)
PTR(__rom_data_start)
PTR(__ram_data_start)
PTR(__ram_data_end)
PTR(__exception_handlers)
PTR(init_flag)

// -------------------------------------------------------------------------
// Interrupt vector tables.
// These tables contain the isr, data and object pointers used to deliver
// interrupts to user code.

// Despite appearances, their sizes are not #defines, but .equ symbols
// generated by magic without proper dependencies in arm.inc
// Recompiling will not DTRT without manual intervention.

        .data

init_flag:
        .balign 4
        .long   0

// -------------------------------------------------------------------------
// Temporary interrupt stack
        
        .section ".bss"

// Small stacks, only used for saving information between CPU modes
__exception_stack_base: 
        .rept   32
        .long   0
        .endr
__exception_stack:
        .rept   32
        .long   0
        .endr

        .balign 16
__startup_stack_base:
        .rept 10 * 1024
        .byte 0
        .endr
        .balign 16
__startup_stack:


// --------------------------------------------------------------------------
//  end of vectors.S