crt0.tri

UCOS II源码 内含SOURCE 解压后使用

;
; 		- crto.tri -
;
; Startup module for MicroC/OS-II RTOS
; This module was mostly re-written because original module
; not well adapted to Micro C/OS-II needs.
;
; Written : Andre Gompel 08/99
; Last change: A.Gompel	 01/03/00
;


#include <RegDef.h>
#include "TC10GP.h"


	.extern	main, trap_vectors

ctxcount .equ    128
		    
	.data
	.globl	sdata
sdata:
	.strz  "sdata"

	.section ".stack","a"
	.align 8
	.space	1024
	.globl TopOfStack
TopOfStack:

	.section ".intstack","a"
	.align 8
	.space	128
	.globl TopOfIntStack
TopOfIntStack:

	.section ".contexts","a"
	.align 64
CSAs:
	.strz	"CSAs start"
	.text
	.align 4

	.globl	_start	
_start:
	disable
	mov.u	d2,psw_cde | psw_gw | psw_io | psw_prs
	mtcr	(PSW & 0xffff),d2
	isync


	mov	d2,0
	mtcr	(PCXI & 0xffff),d2	; PCXI = 0
	isync

	LD_DREG	d2, trap_vectors
    	mtcr	(BTV & 0xffff), d2
    	isync

	LD_DREG	d2, (0xd0007fff-3)	; Initialize TriCore Interrupt Stack pointer.
    	mtcr	(ISP & 0xffff), d2	;
    	isync				

	LD_AREG	a9,(0xd0007eff-3)

	LD_AREG sp, (0xd0007dff-3) 	; Initialize stack pointer TOS
			       		; reserve 64 words for IS

	LD_DREG d2, start_ctxts
	extr.u	d3,d2,6,16
	sh	d4,d2,-12
	movh	d5,0x000f
	and16	d4,d5
	or16	d3,d4
	add	d4,d3,1			/* d4 is (PCX) of NEXT block */

	mtcr	(FCX & 0xffff),d3	/* FCX points to first block. */
	isync

	mov.a	a3,d2			/* Address of first block */
	lea	a4, ctxcount-2

initCSAs:
	st.w	[a3+]64,d4		/* Link to NEXT block, incr ptr. */
	add16	d4,1			/* Increment link word. */
	loop16	a4,initCSAs		/* repeat till done */
	 				/* Loop instruction test for zero before decrement */
	add	d3,d4,-1
	mtcr	(LCX & 0xffff), d3	/* Limit reg points to first EXC block */
	isync

	xor	d0,d0,d0
set_sys_clk:	       			
	LD_AREG	a4, PLLCLC		; If default switches, osc=16e6 Hz, then Fsys=64e6 hz
	st.w	[a4],d0			; will result to PLLCLC=0x0000'1300

	LD_AREG a4, __ghsend_bss
	LD_AREG	a2, __ghsbegin_bss
	.globl clr_bss
clr_bss:				; Now clear bss
	st.b	[a2+], d0
	jne.a	a2,a4, clr_bss
	call	iob_init		; Specific GHS: initialize I/O
	
	mov	d4,d8
	LD_AREG a2, main
        ji	a2