📄 regdefb.h
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#define ASC0_FDV REGDEF(ASC0_Base + 0x18) /* ASC0 Fractional Divider Register */
#define ASC0_BG REGDEF(ASC0_Base + 0x14) /* ASC0 Baudrate Generator/Reload Register */
#define ASC0_CON REGDEF(ASC0_Base + 0x10) /* ASC0 Control Register */
#define ASC0_ID REGDEF(ASC0_Base + 0x08) /* ASC0 ID Register */
#define ASC0_PISEL REGDEF(ASC0_Base + 0x04) /* ASC0 Input Selection Register */
#define ASC0_CLC REGDEF(ASC0_Base + 0x00) /* ASC0 Clock Control Register */
/* */
/* ********** GPTU0 */
#define GPTU0_Base 0xf0000600 /* GPTU0 block base address */
#define GPTU0_GTSRC0 REGDEF(GPTU0_Base + 0xfc) /* GPT Service Request Node 0 */
#define GPTU0_GTSRC1 REGDEF(GPTU0_Base + 0xf8) /* GPT Service Request Node 1 */
#define GPTU0_GTSRC2 REGDEF(GPTU0_Base + 0xf4) /* GPT Service Request Node 2 */
#define GPTU0_GTSRC3 REGDEF(GPTU0_Base + 0xf0) /* GPT Service Request Node 3 */
#define GPTU0_GTSRC4 REGDEF(GPTU0_Base + 0xec) /* GPT Service Request Node 4 */
#define GPTU0_GTSRC5 REGDEF(GPTU0_Base + 0xe8) /* GPT Service Request Node 5 */
#define GPTU0_GTSRC6 REGDEF(GPTU0_Base + 0xe4) /* GPT Service Request Node 6 */
#define GPTU0_GTSRC7 REGDEF(GPTU0_Base + 0xe0) /* GPT Service Request Node 7 */
#define GPTU0_GTSRSEL REGDEF(GPTU0_Base + 0xdc) /* GPT Service Request Source Selection Register */
#define GPTU0_T012RUN REGDEF(GPTU0_Base + 0x60) /* Timers T0, T1 and T2 Run Control Register */
#define GPTU0_T2RC1 REGDEF(GPTU0_Base + 0x5c) /* Timer T2 Reload/Capture Register 1 */
#define GPTU0_T2RC0 REGDEF(GPTU0_Base + 0x58) /* Timer T2 Reload/Capture Register 0 */
#define GPTU0_T2 REGDEF(GPTU0_Base + 0x54) /* Timer T2 Count Register */
#define GPTU0_T1RCBA REGDEF(GPTU0_Base + 0x50) /* Timer T1 Reload Register(T1RC,T1RB,T1RA) */
#define GPTU0_T1RDCBA REGDEF(GPTU0_Base + 0x4c) /* Timer T1 Reload Register(T1RD,T1RC,T1RB,T1RA) */
#define GPTU0_T1CBA REGDEF(GPTU0_Base + 0x48) /* Timer T1 Count Register(T1RC,T1RB,T1RA) */
#define GPTU0_T1DCBA REGDEF(GPTU0_Base + 0x44) /* Timer T1 Count Register(T1RD,T1RC,T1RB,T1RA) */
#define GPTU0_T0RCBA REGDEF(GPTU0_Base + 0x40) /* Timer T0 Reload Register(T1RC,T1RB,T1RA) */
#define GPTU0_T0RDCBA REGDEF(GPTU0_Base + 0x3c) /* Timer T0 Reload Register(T1RD,T1RC,T1RB,T1RA) */
#define GPTU0_T0CBA REGDEF(GPTU0_Base + 0x38) /* Timer T0 Count Register(T1RC,T1RB,T1RA) */
#define GPTU0_T0DCBA REGDEF(GPTU0_Base + 0x34) /* Timer T0 Count Register(T1RD,T1RC,T1RB,T1RA) */
#define GPTU0_GTOUT REGDEF(GPTU0_Base + 0x30) /* GPT Output Register */
#define GPTU0_GTOSEL REGDEF(GPTU0_Base + 0x2c) /* GPT Output Source Selection Register */
#define GPTU0_T2ES REGDEF(GPTU0_Base + 0x28) /* Timer T2 External Input Edge Selection Register */
#define GPTU0_T2BIS REGDEF(GPTU0_Base + 0x24) /* Timer T2 External Input Selection Register */
#define GPTU0_T2AIS REGDEF(GPTU0_Base + 0x20) /* Timer T2/T2A External Input Selection Register */
#define GPTU0_T2RCCON REGDEF(GPTU0_Base + 0x1c) /* Timer T2 Reload/Capture Register */
#define GPTU0_T2CON REGDEF(GPTU0_Base + 0x18) /* Timer T2 Control Register */
#define GPTU0_T01OTS REGDEF(GPTU0_Base + 0x14) /* Timer T0/T1 Output/Trigger/Serv. Req. Sel. Reg. */
#define GPTU0_T01IRS REGDEF(GPTU0_Base + 0x10) /* Timer T0/T1 Input/Reload Source Selection Reg. */
#define GPTU0_GTID REGDEF(GPTU0_Base + 0x08) /* GPT ID Register */
#define GPTU0_GTCLC REGDEF(GPTU0_Base + 0x00) /* GPT Clock Control Register */
/* */
/* ********** GPTU1 */
#define GPTU1_Base 0xf0000700 /* GPTU1 block base address */
#define GPTU1_GTSRC0 REGDEF(GPTU1_Base + 0xfc) /* GPT Service Request Node 0 */
#define GPTU1_GTSRC1 REGDEF(GPTU1_Base + 0xf8) /* GPT Service Request Node 1 */
#define GPTU1_GTSRC2 REGDEF(GPTU1_Base + 0xf4) /* GPT Service Request Node 2 */
#define GPTU1_GTSRC3 REGDEF(GPTU1_Base + 0xf0) /* GPT Service Request Node 3 */
#define GPTU1_GTSRC4 REGDEF(GPTU1_Base + 0xec) /* GPT Service Request Node 4 */
#define GPTU1_GTSRC5 REGDEF(GPTU1_Base + 0xe8) /* GPT Service Request Node 5 */
#define GPTU1_GTSRC6 REGDEF(GPTU1_Base + 0xe4) /* GPT Service Request Node 6 */
#define GPTU1_GTSRC7 REGDEF(GPTU1_Base + 0xe0) /* GPT Service Request Node 7 */
#define GPTU1_GTSRSEL REGDEF(GPTU1_Base + 0xdc) /* GPT Service Request Source Selection Register */
#define GPTU1_T012RUN REGDEF(GPTU1_Base + 0x60) /* Timers T0, T1 and T2 Run Control Register */
#define GPTU1_T2RC1 REGDEF(GPTU1_Base + 0x5c) /* Timer T2 Reload/Capture Register 1 */
#define GPTU1_T2RC0 REGDEF(GPTU1_Base + 0x58) /* Timer T2 Reload/Capture Register 0 */
#define GPTU1_T2 REGDEF(GPTU1_Base + 0x54) /* Timer T2 Count Register */
#define GPTU1_T1RCBA REGDEF(GPTU1_Base + 0x50) /* Timer T1 Reload Register(T1RC,T1RB,T1RA) */
#define GPTU1_T1RDCBA REGDEF(GPTU1_Base + 0x4c) /* Timer T1 Reload Register(T1RD,T1RC,T1RB,T1RA) */
#define GPTU1_T1CBA REGDEF(GPTU1_Base + 0x48) /* Timer T1 Count Register(T1RC,T1RB,T1RA) */
#define GPTU1_T1DCBA REGDEF(GPTU1_Base + 0x44) /* Timer T1 Count Register(T1RD,T1RC,T1RB,T1RA) */
#define GPTU1_T0RCBA REGDEF(GPTU1_Base + 0x40) /* Timer T0 Reload Register(T1RC,T1RB,T1RA) */
#define GPTU1_T0RDCBA REGDEF(GPTU1_Base + 0x3c) /* Timer T0 Reload Register(T1RD,T1RC,T1RB,T1RA) */
#define GPTU1_T0CBA REGDEF(GPTU1_Base + 0x38) /* Timer T0 Count Register(T1RC,T1RB,T1RA) */
#define GPTU1_T0DCBA REGDEF(GPTU1_Base + 0x34) /* Timer T0 Count Register(T1RD,T1RC,T1RB,T1RA) */
#define GPTU1_GTOUT REGDEF(GPTU1_Base + 0x30) /* GPT Output Register */
#define GPTU1_GTOSEL REGDEF(GPTU1_Base + 0x2c) /* GPT Output Source Selection Register */
#define GPTU1_T2ES REGDEF(GPTU1_Base + 0x28) /* Timer T2 External Input Edge Selection Register */
#define GPTU1_T2BIS REGDEF(GPTU1_Base + 0x24) /* Timer T2 External Input Selection Register */
#define GPTU1_T2AIS REGDEF(GPTU1_Base + 0x20) /* Timer T2/T2A External Input Selection Register */
#define GPTU1_T2RCCON REGDEF(GPTU1_Base + 0x1c) /* Timer T2 Reload/Capture Register */
#define GPTU1_T2CON REGDEF(GPTU1_Base + 0x18) /* Timer T2 Control Register */
#define GPTU1_T01OTS REGDEF(GPTU1_Base + 0x14) /* Timer T0/T1 Output/Trigger/Serv. Req. Sel. Reg. */
#define GPTU1_T01IRS REGDEF(GPTU1_Base + 0x10) /* Timer T0/T1 Input/Reload Source Selection Reg. */
#define GPTU1_GTID REGDEF(GPTU1_Base + 0x08) /* GPT ID Register */
#define GPTU1_GTCLC REGDEF(GPTU1_Base + 0x00) /* GPT Clock Control Register */
/* */
/* ********** EBU */
#define EBU_Base 0xf0000500 /* EBU block base address */
#define EMUCON REGDEF(EBU_Base + 0x88) /* Emulator Configuration Register */
#define EMUBC REGDEF(EBU_Base + 0x84) /* Emulator Bus Configuration Register */
#define EMUAS REGDEF(EBU_Base + 0x80) /* Emulator Address Configuration Register */
#define BUSCON3 REGDEF(EBU_Base + 0x6c) /* External Bus Configuration Register 3 */
#define BUSCON2 REGDEF(EBU_Base + 0x68) /* External Bus Configuration Register 2 */
#define BUSCON1 REGDEF(EBU_Base + 0x64) /* External Bus Configuration Register 1 */
#define BUSCON0 REGDEF(EBU_Base + 0x60) /* External Bus Configuration Register 0 */
#define ADDSEL3 REGDEF(EBU_Base + 0x2c) /* External Address Select Register 3 */
#define ADDSEL2 REGDEF(EBU_Base + 0x28) /* External Address Select Register 2 */
#define ADDSEL1 REGDEF(EBU_Base + 0x24) /* External Address Select Register 1 */
#define ADDSEL0 REGDEF(EBU_Base + 0x20) /* External Address Select Register 0 */
#define DRMSTAT REGDEF(EBU_Base + 0x1c) /* External DRAM Status Register */
#define DRMCON1 REGDEF(EBU_Base + 0x18) /* External DRAM Configuration Register 1 */
#define DRMCON0 REGDEF(EBU_Base + 0x14) /* External DRAM Configuration Register 0 */
#define EBUCON REGDEF(EBU_Base + 0x10) /* EBU Configuration Register */
#define EBUID REGDEF(EBU_Base + 0x08) /* EBU ID Register */
#define EBUCLC REGDEF(EBU_Base + 0x00) /* EBU Clock Control Register */
/* */
/* ********** TCU */
#define TCU_Base 0xf0000400 /* TCU block base address */
#define IOSR REGDEF(TCU_Base + 0x6C) /* Cerberus Status Register */
#define COMDATA REGDEF(TCU_Base + 0x68) /* Cerberus Communication Mode Data Register */
#define JDPID REGDEF(TCU_Base + 0x08) /* Debug/Cerberus ID Register */
/* */
/* ********** STM */
#define STM_Base 0xf0000300 /* STM block base address */
#define SYSTIM7 REGDEF(STM_Base + 0x2c) /* System Timer Bits 55:32 Capture Register */
#define SYSTIM6 REGDEF(STM_Base + 0x28) /* System Timer Bits 55:32 Register */
#define SYSTIM5 REGDEF(STM_Base + 0x24) /* System Timer Bits 51:20 Register */
#define SYSTIM4 REGDEF(STM_Base + 0x20) /* System Timer Bits 47:16 Register */
#define SYSTIM3 REGDEF(STM_Base + 0x1c) /* System Timer Bits 43:12 Register */
#define SYSTIM2 REGDEF(STM_Base + 0x18) /* System Timer Bits 39:08 Register */
#define SYSTIM1 REGDEF(STM_Base + 0x14) /* System Timer Bits 35:04 Register */
#define SYSTIM0 REGDEF(STM_Base + 0x10) /* System Timer Bits 31:00 Register */
#define STMID REGDEF(STM_Base + 0x08) /* System Timer ID Register */
#define STMCLC REGDEF(STM_Base + 0x00) /* System Timer Clock Control Register */
/* */
/* ********** BCU */
#define BCU_Base 0xf0000200 /* BCU block base address */
#define BCUSRC REGDEF(BCU_Base + 0xfc) /* BCU Service Request Node */
#define BCEDAT REGDEF(BCU_Base + 0x28) /* BCU Error Data Capture Register */
#define BCEADD REGDEF(BCU_Base + 0x24) /* BCU Error Address Capture Register */
#define BCECON REGDEF(BCU_Base + 0x20) /* BCU Error Control Register */
#define BCUCON REGDEF(BCU_Base + 0x10) /* BCU Control Register */
#define BCUID REGDEF(BCU_Base + 0x08) /* BCU ID Register */
/* */
/* ********** PWR */
#define PWR_Base 0xf0000000 /* PWR block base address */
#define RTID REGDEF(PWR_Base + 0x78) /* Redesign Identification Register */
#define CHIPID REGDEF(PWR_Base + 0x74) /* Chip Identification Register */
#define MANID REGDEF(PWR_Base + 0x70) /* Manufacturer Identification Register */
#define PLLCLC REGDEF(PWR_Base + 0x40) /* PLL Clock Control Register */
#define PMCSR REGDEF(PWR_Base + 0x34) /* Power Mgmt. Control & Status Register */
#define PMCON REGDEF(PWR_Base + 0x30) /* Power Mgmt. Control Register */
#define NMISR REGDEF(PWR_Base + 0x2c) /* NMI Status Register */
#define WDTSR REGDEF(PWR_Base + 0x28) /* Watchdog Timer Status Register */
#define WDTCON1 REGDEF(PWR_Base + 0x24) /* Watchdog Timer Control Register 1 */
#define WDTCON0 REGDEF(PWR_Base + 0x20) /* Watchdog Timer Control Register 0 */
#define RSTSR REGDEF(PWR_Base + 0x14) /* Reset Status Register */
#define RSTREQ REGDEF(PWR_Base + 0x10) /* Reset Request Register */
#define PWRID REGDEF(PWR_Base + 0x08) /* PWR Module ID Register */
/* ********** Memories */
#define DSRAM_Base 0xd0000000 /* base of local data SRAM */
#define DSRAM_End REGDEF(0xd0007fff) /* end of local data SRAM */
#define CSRAM_Base 0xc0000000 /* base of local code SRAM */
#define CSRAM_End REGDEF(0xc0001fff) /* end of local code SRAM */
#define LOC_CRAM_CACHE_Base 0x80000000 /* base of local bulk code SRAM, */
/* cacheable area (Rider B: 192 Kbyte) */
#define LOC_CRAM_CACHE_End REGDEF(0x8002FFFF) /* end of local bulk code SRAM, cacheable area */
#define LOC_CRAM_Base 0xc8000000 /* base of local bulk code SRAM, */
/* non-cacheable area (Rider B: 192 Kbyte) */
#define LOC_CRAM_End REGDEF(0xc802FFFF) /* end of local bulk code SRAM, non-cacheable area */
#define PCPRAM_Base 0xf0010000 /* base of PCP data memory */
#define PCPRAM_End REGDEF(0xf00107ff) /* end of PCP data memory */
#define PCPCODE_Base 0xf0020000 /* base of PCP code memory */
#define PCPCODE_End REGDEF(0xf00203ff) /* end of PCP code memory */
/* */
/* ********** other definitions */
#define _SP REGDEF(CSFR_Base + 0xffa8) /* Address Register A10 (Stack Pointer) */
#define RA REGDEF(CSFR_Base + 0xffac) /* Address Register A11 (Return Address Register) */
#ifdef REG
/* needed only for register tests otherwise assembler croaks. */
#define RA0 REGDEF(CSFR_Base + 0xff80)
#define RA1 REGDEF(CSFR_Base + 0xff84)
#define RA2 REGDEF(CSFR_Base + 0xff88)
#define RA3 REGDEF(CSFR_Base + 0xff8c)
#define RA4 REGDEF(CSFR_Base + 0xff90)
#define RA5 REGDEF(CSFR_Base + 0xff94)
#define RA6 REGDEF(CSFR_Base + 0xff98)
#define RA7 REGDEF(CSFR_Base + 0xff9c)
#define RA8 REGDEF(CSFR_Base + 0xffa0)
#define RA9 REGDEF(CSFR_Base + 0xffa4)
#define RA10 REGDEF(CSFR_Base + 0xffa8)
#define RA11 REGDEF(CSFR_Base + 0xffac)
#define RA12 REGDEF(CSFR_Base + 0xffb0)
#define RA13 REGDEF(CSFR_Base + 0xffb4)
#define RA14 REGDEF(CSFR_Base + 0xffb8)
#define RA15 REGDEF(CSFR_Base + 0xffbc)
#define RD0 REGDEF(CSFR_Base + 0xff00)
#define RD1 REGDEF(CSFR_Base + 0xff04)
#define RD2 REGDEF(CSFR_Base + 0xff08)
#define RD3 REGDEF(CSFR_Base + 0xff0c)
#define RD4 REGDEF(CSFR_Base + 0xff10)
#define RD5 REGDEF(CSFR_Base + 0xff14)
#define RD6 REGDEF(CSFR_Base + 0xff18)
#define RD7 REGDEF(CSFR_Base + 0xff1c)
#define RD8 REGDEF(CSFR_Base + 0xff20)
#define RD9 REGDEF(CSFR_Base + 0xff24)
#define RD10 REGDEF(CSFR_Base + 0xff28)
#define RD11 REGDEF(CSFR_Base + 0xff2c)
#define RD12 REGDEF(CSFR_Base + 0xff30)
#define RD13 REGDEF(CSFR_Base + 0xff34)
#define RD14 REGDEF(CSFR_Base + 0xff38)
#define RD15 REGDEF(CSFR_Base + 0xff3c)
#define DPTCON REGDEF(0x0f00049c)
#define STMSRC REGDEF(0x0f000300)
#endif
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