📄 regdefb.h
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/* */
/* Set up for Rider B - CS 9/11/98 */
/* Special Function Register (SFR) definitions */
/* */
/* WARNING: DO NOT INCLUDE THIS FILE DIRECTLY. */
/* Include "RegDef.h" and let it do the work. */
/* ********** Core SFRs */
#define CSFR_Base 0xffff0000 /* base address of the core SFRs */
#define PCXI REGDEF(CSFR_Base + 0xfe00) /* Previous Context Info Register */
#define PSW REGDEF(CSFR_Base + 0xfe04) /* Program Status Word */
#define PC REGDEF(CSFR_Base + 0xfe08) /* Program Counter */
#define SYSCON REGDEF(CSFR_Base + 0xfe14) /* System Configuration Control Register */
#define BIV REGDEF(CSFR_Base + 0xfe20) /* Base Addr of Interrupt Vector Table */
#define BTV REGDEF(CSFR_Base + 0xfe24) /* Base Addr of Trap Vector Table */
#define ISP REGDEF(CSFR_Base + 0xfe28) /* Interrupt Stack Pointer */
#define ICR REGDEF(CSFR_Base + 0xfe2c) /* Interrupt Unit Control Register */
#define FCX REGDEF(CSFR_Base + 0xfe38) /* Free CSA List Head Pointer */
#define LCX REGDEF(CSFR_Base + 0xfe3c) /* Free CSA List Limit Pointer */
#define DBGSR REGDEF(CSFR_Base + 0xfd00) /* Debug Status Register */
#define EXEVT REGDEF(CSFR_Base + 0xfd08) /* External Break Input Event Specifier */
#define CREVT REGDEF(CSFR_Base + 0xfd0c) /* Emulator Resource Protection Event Specifier */
#define SWEVT REGDEF(CSFR_Base + 0xfd10) /* Software Break Event Specifier */
#define TR0EVT REGDEF(CSFR_Base + 0xfd20) /* Trigger Event 0 Specifier */
#define TR1EVT REGDEF(CSFR_Base + 0xfd24) /* Trigger Event 1 Specifier */
#define DSR REGDEF(DBGSR) /* (alias) Debug Status Register */
/* */
/* ********** GPRs */
#define D0 REGDEF(0xffffff00) /* Data Register D0 */
#define D1 REGDEF(0xffffff04) /* Data Register D1 */
#define D2 REGDEF(0xffffff08) /* Data Register D2 */
#define D3 REGDEF(0xffffff0c) /* Data Register D3 */
#define D4 REGDEF(0xffffff10) /* Data Register D4 */
#define D5 REGDEF(0xffffff14) /* Data Register D5 */
#define D6 REGDEF(0xffffff18) /* Data Register D6 */
#define D7 REGDEF(0xffffff1c) /* Data Register D7 */
#define D8 REGDEF(0xffffff20) /* Data Register D8 */
#define D9 REGDEF(0xffffff24) /* Data Register D9 */
#define D10 REGDEF(0xffffff28) /* Data Register D10 */
#define D11 REGDEF(0xffffff2c) /* Data Register D11 */
#define D12 REGDEF(0xffffff30) /* Data Register D12 */
#define D13 REGDEF(0xffffff34) /* Data Register D13 */
#define D14 REGDEF(0xffffff38) /* Data Register D14 */
#define D15 REGDEF(0xffffff3c) /* Data Register D15 */
/* */
#define A0 REGDEF(0xffffff80) /* Address Register A0 */
#define A1 REGDEF(0xffffff84) /* Address Register A1 */
#define A2 REGDEF(0xffffff88) /* Address Register A2 */
#define A3 REGDEF(0xffffff8c) /* Address Register A3 */
#define A4 REGDEF(0xffffff90) /* Address Register A4 */
#define A5 REGDEF(0xffffff94) /* Address Register A5 */
#define A6 REGDEF(0xffffff98) /* Address Register A6 */
#define A7 REGDEF(0xffffff9c) /* Address Register A7 */
#define A8 REGDEF(0xffffffa0) /* Address Register A8 */
#define A9 REGDEF(0xffffffa4) /* Address Register A9 */
#define A10 REGDEF(0xffffffa8) /* Address Register A10 (Stack Pointer) */
#define A11 REGDEF(0xffffffac) /* Address Register A11 (Return Address Register) */
#define A12 REGDEF(0xffffffb0) /* Address Register A12 */
#define A13 REGDEF(0xffffffb4) /* Address Register A13 */
#define A14 REGDEF(0xffffffb8) /* Address Register A14 */
#define A15 REGDEF(0xffffffbc) /* Address Register A15 */
/* */
#define DPR0_0L REGDEF(CSFR_Base + 0xc000) /* Data Seg. Prot. Reg. 0, Set 0, lower */
#define DPR0_0U REGDEF(CSFR_Base + 0xc004) /* Data Seg. Prot. Reg. 0, Set 0, upper */
#define DPR0_1L REGDEF(CSFR_Base + 0xc008) /* Data Seg. Prot. Reg. 1, Set 0, lower */
#define DPR0_1U REGDEF(CSFR_Base + 0xc00c) /* Data Seg. Prot. Reg. 1, Set 0, upper */
#define DPR0_2L REGDEF(CSFR_Base + 0xc010) /* Data Seg. Prot. Reg. 2, Set 0, lower */
#define DPR0_2U REGDEF(CSFR_Base + 0xc014) /* Data Seg. Prot. Reg. 2, Set 0, upper */
#define DPR0_3L REGDEF(CSFR_Base + 0xc018) /* Data Seg. Prot. Reg. 3, Set 0, lower */
#define DPR0_3U REGDEF(CSFR_Base + 0xc01c) /* Data Seg. Prot. Reg. 3, Set 0, upper */
#define DPR1_0L REGDEF(CSFR_Base + 0xc400) /* Data Seg. Prot. Reg. 0, Set 1, lower */
#define DPR1_0U REGDEF(CSFR_Base + 0xc404) /* Data Seg. Prot. Reg. 0, Set 1, upper */
#define DPR1_1L REGDEF(CSFR_Base + 0xc408) /* Data Seg. Prot. Reg. 1, Set 1, lower */
#define DPR1_1U REGDEF(CSFR_Base + 0xc40c) /* Data Seg. Prot. Reg. 1, Set 1, upper */
#define DPR1_2L REGDEF(CSFR_Base + 0xc410) /* Data Seg. Prot. Reg. 2, Set 1, lower */
#define DPR1_2U REGDEF(CSFR_Base + 0xc414) /* Data Seg. Prot. Reg. 2, Set 1, upper */
#define DPR1_3L REGDEF(CSFR_Base + 0xc418) /* Data Seg. Prot. Reg. 3, Set 1, lower */
#define DPR1_3U REGDEF(CSFR_Base + 0xc41c) /* Data Seg. Prot. Reg. 3, Set 1, upper */
/* */
#define CPR0_0L REGDEF(CSFR_Base + 0xd000) /* Code Seg. Prot. Reg. 0, Set 0, lower */
#define CPR0_0U REGDEF(CSFR_Base + 0xd004) /* Code Seg. Prot. Reg. 0, Set 0, upper */
#define CPR0_1L REGDEF(CSFR_Base + 0xd008) /* Code Seg. Prot. Reg. 1, Set 0, lower */
#define CPR0_1U REGDEF(CSFR_Base + 0xd00c) /* Code Seg. Prot. Reg. 1, Set 0, upper */
#define CPR1_0L REGDEF(CSFR_Base + 0xd400) /* Code Seg. Prot. Reg. 0, Set 1, lower */
#define CPR1_0U REGDEF(CSFR_Base + 0xd404) /* Code Seg. Prot. Reg. 0, Set 1, upper */
#define CPR1_1L REGDEF(CSFR_Base + 0xd408) /* Code Seg. Prot. Reg. 1, Set 1, lower */
#define CPR1_1U REGDEF(CSFR_Base + 0xd40c) /* Code Seg. Prot. Reg. 1, Set 1, upper */
/* */
#define DPM0 REGDEF(CSFR_Base + 0xe000) /* Data Protection Mode Register, Set 0 (4 bytes) */
#define DPM1 REGDEF(CSFR_Base + 0xe080) /* Data Protection Mode Register, Set 1 (4 bytes) */
#define CPM0 REGDEF(CSFR_Base + 0xe200) /* Code Protection Mode Register, Set 0 (2 bytes) */
#define CPM1 REGDEF(CSFR_Base + 0xe280) /* Code Protection Mode Register, Set 1 (2 bytes) */
/* */
/* ********** CPS */
#define CPS_Base 0xfffeff00 /* CPS block base address */
#define CPUCLC REGDEF(CPS_Base + 0x00) /* CPU CLC register */
#define CPUID REGDEF(CPS_Base + 0x08) /* CPU ID Register */
#define SBSRC0 REGDEF(CPS_Base + 0xbc) /* Software Breakpoint Service Request Node */
#define CPUSRC3 REGDEF(CPS_Base + 0xf0) /* CPU Service Request Node 3 */
#define CPUSRC2 REGDEF(CPS_Base + 0xf4) /* CPU Service Request Node 2 */
#define CPUSRC1 REGDEF(CPS_Base + 0xf8) /* CPU Service Request Node 1 */
#define CPUSRC0 REGDEF(CPS_Base + 0xfc) /* CPU Service Request Node 0 */
/* ********** PMU */
#define PMU_Base 0xc7ffff00 /* PMU config block base address */
#define PMUID REGDEF(PMU_Base + 0x08) /* Local Program Memory Register */
#define PMUCON0 REGDEF(PMU_Base + 0x10) /* Local Program Memory Register */
#define PMUCON1 REGDEF(PMU_Base + 0x14) /* Local Program Memory Register */
/* */
/* ********** DMU */
#define DMU_Base 0xd7ffff00 /* DMU config block base address */
#define DMUID REGDEF(DMU_Base + 0x08) /* DMU Identification Register */
#define DMUCON REGDEF(DMU_Base + 0x10) /* DMU Configuration Register */
#define DMUSTR REGDEF(DMU_Base + 0x18) /* DMU Synchronous Trap Flag Register */
#define DMUATR REGDEF(DMU_Base + 0x20) /* DMU Asynchronous Trap Flag Register */
/* */
/* ********** PCP */
#define PCP_Base 0xf0003f00 /* PCP control block base address */
#define PCPSRC0 REGDEF(PCP_Base + 0xfc) /* PCP Service Request Node 0 */
#define PCPSRC1 REGDEF(PCP_Base + 0xf8) /* PCP Service Request Node 1 */
#define PCPSRC2 REGDEF(PCP_Base + 0xf4) /* PCP Service Request Node 2 */
#define PCPSRC3 REGDEF(PCP_Base + 0xf0) /* PCP Service Request Node 3 */
#define PCPICR REGDEF(PCP_Base + 0x20) /* PCP Interrupt Control Register */
#define PCPES REGDEF(PCP_Base + 0x14) /* PCP Captured Error Status Register */
#define PCPCS REGDEF(PCP_Base + 0x10) /* PCP Control/Status Register */
#define PCPID REGDEF(PCP_Base + 0x08) /* PCP ID Register */
#define PCPCLC REGDEF(PCP_Base + 0x00) /* PCP Clock Control Register */
/* */
/* ********** Parallel IO Port P0 */
#define P0_Base 0xf0002800 /* P0 block base address */
#define P0_ALTSEL1 REGDEF(P0_Base + 0x48) /* P0 Alternate Select Register 0 */
#define P0_ALTSEL0 REGDEF(P0_Base + 0x44) /* P0 Alternate Select Register 1 */
#define P0_PUDEN REGDEF(P0_Base + 0x2C) /* P0 Pull up/down Enable Register */
#define P0_PUDSEL REGDEF(P0_Base + 0x28) /* P0 Pull up/down Select Register */
#define P0_OD REGDEF(P0_Base + 0x1C) /* P0 Open Drain control Register */
#define P0_DIR REGDEF(P0_Base + 0x18) /* P0 Port Direction Register */
#define P0_IN REGDEF(P0_Base + 0x14) /* P0 Data Input Register */
#define P0_OUT REGDEF(P0_Base + 0x10) /* P0 Data Output Register */
/*P0ID .equ P0_Base + 0x08 ; P0 Module ID Register */
/* ********** Parallel IO Port P1 */
#define P1_Base 0xf0002900 /* P1 block base address */
#define P1_ALTSEL1 REGDEF(P1_Base + 0x48) /* P1 Alternate Select Register 0 */
#define P1_ALTSEL0 REGDEF(P1_Base + 0x44) /* P1 Alternate Select Register 1 */
#define P1_PUDEN REGDEF(P1_Base + 0x2C) /* P1 Pull up/down Enable Register */
#define P1_PUDSEL REGDEF(P1_Base + 0x28) /* P1 Pull up/down Select Register */
#define P1_OD REGDEF(P1_Base + 0x1C) /* P1 Open Drain control Register */
#define P1_DIR REGDEF(P1_Base + 0x18) /* P1 Port Direction Register */
#define P1_IN REGDEF(P1_Base + 0x14) /* P1 Data Input Register */
#define P1_OUT REGDEF(P1_Base + 0x10) /* P1 Data Output Register */
/*P1ID .equ P1_Base + 0x08 ; P1 Module ID Register */
/* ********** Parallel IO Port P2 */
#define P2_Base 0xf0002A00 /* P2 block base address */
#define P2_ALTSEL1 REGDEF(P2_Base + 0x48) /* P2 Alternate Select Register 0 */
#define P2_ALTSEL0 REGDEF(P2_Base + 0x44) /* P2 Alternate Select Register 1 */
#define P2_PUDEN REGDEF(P2_Base + 0x2C) /* P2 Pull up/down Enable Register */
#define P2_PUDSEL REGDEF(P2_Base + 0x28) /* P2 Pull up/down Select Register */
#define P2_OD REGDEF(P2_Base + 0x1C) /* P2 Open Drain control Register */
#define P2_DIR REGDEF(P2_Base + 0x18) /* P2 Port Direction Register */
#define P2_IN REGDEF(P2_Base + 0x14) /* P2 Data Input Register */
#define P2_OUT REGDEF(P2_Base + 0x10) /* P2 Data Output Register */
/*P2ID .equ P2_Base + 0x08 ; P2 Module ID Register */
/* ********** SSC0 */
#define SSC0_Base 0xf0000A00 /* SSC0 block base address */
#define SSC0ESRC REGDEF(SSC0_Base + 0xfc) /* SSC0 Error Service Request Node */
#define SSC0RSRC REGDEF(SSC0_Base + 0xf8) /* SSC0 Receive Service Request Node */
#define SSC0TSRC REGDEF(SSC0_Base + 0xf4) /* SSC0 Transmit Service Request Node */
#define SSC0RB REGDEF(SSC0_Base + 0x24) /* SSC0 Receive Buffer Register */
#define SSC0TB REGDEF(SSC0_Base + 0x20) /* SSC0 Transmit Buffer Register */
#define SSC0BR REGDEF(SSC0_Base + 0x14) /* SSC0 Baudrate Timer Reload Register */
#define SSC0CON REGDEF(SSC0_Base + 0x10) /* SSC0 Control Register */
#define SSC0ID REGDEF(SSC0_Base + 0x08) /* SSC0 ID Register */
#define SSC0PISEL REGDEF(SSC0_Base + 0x04) /* SSC0 Peripheral Input Select Register */
#define SSC0CLC REGDEF(SSC0_Base + 0x00) /* SSC0 Clock Control Register */
/* */
/* ********** ASC1 */
#define ASC1_Base 0xf0000900 /* ASC1 block base address */
#define ASC1_SRCTBC REGDEF(ASC1_Base + 0xfc) /* ASC1 Transmit Buffer Service Request Node */
#define ASC1_SRCE REGDEF(ASC1_Base + 0xf8) /* ASC1 Error Service Request Node */
#define ASC1_SRCR REGDEF(ASC1_Base + 0xf4) /* ASC1 Receive Service Request Node */
#define ASC1_SRCT REGDEF(ASC1_Base + 0xf0) /* ASC1 Transmit Service Request Node */
#define ASC1_RBUF REGDEF(ASC1_Base + 0x24) /* ASC1 Receive Buffer Register */
#define ASC1_TBUF REGDEF(ASC1_Base + 0x20) /* ASC1 Transmit BUffer Register */
#define ASC1_PMW REGDEF(ASC1_Base + 0x1c) /* ASC1 IrDA Pulse Mode & Width Register */
#define ASC1_FDV REGDEF(ASC1_Base + 0x18) /* ASC1 Fractional Divider Register */
#define ASC1_BG REGDEF(ASC1_Base + 0x14) /* ASC1 Baudrate Generator/Reload Register */
#define ASC1_CON REGDEF(ASC1_Base + 0x10) /* ASC1 Control Register */
#define ASC1_ID REGDEF(ASC1_Base + 0x08) /* ASC1 ID Register */
#define ASC1_PISEL REGDEF(ASC1_Base + 0x04) /* ASC1 Input Selection Register */
#define ASC1_CLC REGDEF(ASC1_Base + 0x00) /* ASC1 Clock Control Register */
/* */
/* ********** ASC0 */
#define ASC0_Base 0xf0000800 /* ASC0 block base address */
#define ASC0_SRCTB REGDEF(ASC0_Base + 0xfc) /* ASC0 Transmit Buffer Service Request Node */
#define ASC0_SRCE REGDEF(ASC0_Base + 0xf8) /* ASC0 Error Service Request Node */
#define ASC0_SRCR REGDEF(ASC0_Base + 0xf4) /* ASC0 Receive Service Request Node */
#define ASC0_SRCT REGDEF(ASC0_Base + 0xf0) /* ASC0 Transmit Service Request Node */
#define ASC0_RBUF REGDEF(ASC0_Base + 0x24) /* ASC0 Receive Buffer Register */
#define ASC0_TBUF REGDEF(ASC0_Base + 0x20) /* ASC0 Transmit Buffer Register */
#define ASC0_PMW REGDEF(ASC0_Base + 0x1c) /* ASC0 IrDA Pulse Mode & Width Register */
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