📄 ycbcr422pl_to_rgb565_h.asm
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* setup code. *
* *
* Instructions have been scheduled to minimize fetch-packet padding *
* NOPs. Only 3 padding NOPs and 1 explicit NOP remain. *
* *
* ASSUMPTIONS *
* An even number of luma samples needs to be processed. *
* *
* The output image must be word aligned. *
* *
* NOTES *
* No bank conflicts occur. *
* *
* Codesize is 512 bytes. *
* *
* On average, one bank per cycle is accessed on a C6201 in the loop, *
* with 1 cycle of 6 accessing no banks, and 1 cycle accessing two. *
* *
* The kernel requires 14 words of stack space. *
* *
* SOURCE *
* Poynton, Charles et al. "The Color FAQ," 1999. *
* http://home.inforamp.net/~poynton/ColorFAQ.html *
* *
* ------------------------------------------------------------------------- *
* Copyright (c) 1999 Texas Instruments, Incorporated. *
* All Rights Reserved. *
* ========================================================================= *
.sect ".data:copyright_h"
_Copyright: .string "Copyright (C) 1999 Texas Instruments Incorporated. "
.string "All Rights Reserved.",0
.sect ".text:hand"
.global _yc2rgb16
_yc2rgb16:
; =============== SYMBOLIC REGISTER ASSIGNMENTS: ARGUMENTS ================ ;
.asg A4, A_coef ; Coefficients table
.asg B4, B_y_data ; Pointer to luma
.asg A6, A_cb_data ; Pointer to B-Y
.asg B6, B_cr_data ; Pointer to R-Y
.asg A8, A_rgb_data ; Pointer to RGB output
.asg B8, B_num_pix ; # of pixels to process
; ================= SYMBOLIC REGISTER ASSIGNMENTS: SETUP ================== ;
.asg B15, B_SP ; Stack pointer, B datapath
.asg A3, A_SP ; Stack pointer, A datapath
.asg B0, B_csr ; CSR's value
.asg B1, B_noGIE ; CSR w/ GIE bit cleared
.asg B2, B_irp ; IRP's value
.asg A0, A_csr ; Copy of CSR's value
.asg B3, B_ret ; Return address
.asg B7, B_coef ; Twin coefficients ptr.
.asg A13, A_rcr ; Cr's contribution to Red
.asg B14, B_bcb ; Cb's contribution to Blu
.asg A5, A_gcr_ ; Cr's contribution to Grn
.asg A5, A_gcr ; A_gcr_ << 16
.asg B5, B_gcb_ ; Cb's contribution to Grn
.asg B5, B_gcb ; B_gcb_ << 16
.asg A1, A_lneg ; luma coeff[0] < 0
; ================= SYMBOLIC REGISTER ASSIGNMENTS: KERNEL ================= ;
.asg B0, B_p ; Prolog collapse counter
.asg A2, A_i ; Loop trip counter
.asg A10, A_y_ptr ; Luma data pointer
.asg B15, B_cb_ptr ; B-Y data pointer
.asg B6, B_cr_ptr ; R-Y data pointer
.asg B11, B_rgb_ptr ; RGB output data pointer
.asg B12, B_k32_k128 ; Constant 0x00200080
.asg A11, A_k32_k128 ; Constant 0x00200080
.asg A12, A_one_lum ; Constant 1 packed w/coeff[0]
.asg A13, A_gcr_rcr ; coeff[3], coeff[1] packed
.asg B14, B_gcb_bcb ; coeff[2], coeff[4] packed
.asg B10, B_y_bias ; -((128<<13) + 16*coeff[0])
.asg B13, B_ms5 ; Mask: upper 5 bits
.asg A14, A_ms6 ; Mask: upper 6 bits
.asg A15, A_sflip ; Sign-flip const 0x84108410
.asg A0, A_y0 ; y0 value from y_data[]
.asg B4, B_y1 ; y1 value from y_data[]
.asg B1, B_cb_ ; cb value prior to level shift
.asg A3, A_cr_ ; cr value prior to level shift
.asg B3, B_cb ; level-shifted cb value.
.asg A4, A_cr ; level-shifted cr value
.asg B5, B_y1t_ ; scaled y1, before level shift
.asg A3, A_y0t_ ; scaled y0, before level shift
.asg B9, B_y1t ; scaled, level-shifted y1
.asg A5, A_y0t ; scaled, level-shifted y0
.asg B3, B_bt ; Scaled blue color-diff
.asg B1, B_gt_ ; Scaled green color-diff (a)
.asg A8, A_gt_ ; Scaled green color-diff (b)
.asg A6, A_gt ; Scaled green color-diff
.asg A9, A_rt ; Scaled red color-diff
.asg B1, B_r1 ; Pixel 1 red (16Q16)
.asg B3, B_g1 ; Pixel 1 grn (17Q15)
.asg B4, B_b1 ; Pixel 1 blu (16Q16)
.asg A3, A_r0 ; Pixel 0 red (16Q16)
.asg A5, A_g0 ; Pixel 0 grn (17Q15)
.asg A0, A_b0 ; Pixel 0 blu (16Q16)
.asg B5, B_r1s ; Saturated pixel 1 red (5Q27)
.asg B4, B_g1s ; Saturated pixel 1 grn (6Q26)
.asg B5, B_b1s ; Saturated pixel 1 blu (5Q27)
.asg A1, A_r0s ; Saturated pixel 0 red (5Q27)
.asg A4, A_g0s ; Saturated pixel 0 grn (6Q26)
.asg A4, A_b0s ; Saturated pixel 0 blu (5Q27)
.asg B8, B_r1t ; Truncated pixel 1 red
.asg B7, B_g1t ; Truncated pixel 1 grn
.asg B2, B_b1t ; Truncated pixel 1 blu
.asg A7, A_r0t ; Truncated pixel 0 red
.asg A4, A_g0t ; Truncated pixel 0 grn
.asg A5, A_b0t ; Truncated pixel 0 blu
.asg B2, B_g1f ; Pixel 1 grn in final position
.asg B1, B_b1f ; Pixel 1 blu in final position
.asg B8, B_r_b1 ; Pixel 1 red, blue merged
.asg B4, B_rgb1 ; Pixel 1 red, grn, blu merged
.asg A3, A_g0f ; Pixel 0 grn in final position
.asg A6, A_b0f ; Pixel 0 blu in final position
.asg A7, A_r_b0 ; Pixel 0 red, blue merged
.asg A9, A_rgb0_ ; Pixel 0 red, grn, blu merged
.asg A6, A_rgb0 ; Pixel 0 in low half word
.asg B5, B_rgb_ ; Combined pixels pre-sign-fix
.asg B7, B_rgb ; Combined pixels w/ sign-fix
; ========================================================================= ;
; Stack frame. 14 words: A10..A15, B10..B14, B3, CSR, IRP
;-
STW .D2T1 A15, *B_SP--[14] ; Save A15, get stack
|| MVC .S2 CSR, B_csr ; Capture CSR's state
|| MV .L2X A_coef, B_coef ; Twin coef pointer
|| MVK .S1 0xFFFF8410, A_sflip ; Sign-flip cst, low
MV .S1X B_SP, A_SP ; Twin Stack Pointer
|| AND .L2 B_csr, -2, B_noGIE ; Clear GIE
|| LDHU .D1T2 *A_coef[2], B_gcb_ ; gcb = coeff[2]
|| LDHU .D2T1 *B_coef[3], A_gcr_ ; gcb = coeff[3]
;-
STW .D1T1 A14, *+A_SP[12] ; Save A14
|| STW .D2T2 B14, *+B_SP[11] ; Save B14
|| MVC .S2 B_noGIE, CSR ; Disable interrupts
|| ZERO .L1 A_ms6 ; Mask 6, low
; ===== Interrupts masked here =====
STW .D1T1 A13, *+A_SP[10] ; Save A13
|| STW .D2T2 B13, *+B_SP[ 9] ; Save B13
|| MVC .S2 IRP, B_irp ; Capture IRP's state
|| ZERO .L2 B_ms5 ; Mask 5, low
;-
STW .D1T1 A12, *+A_SP[ 8] ; Save A12
|| STW .D2T2 B12, *+B_SP[ 7] ; Save B12
|| MVC .S2 B_SP, IRP ; Save SP in IRP
|| MVKLH .S1 0xFC00, A_ms6 ; Mask 6, high
LDH .D1T1 *A_coef[0], A_one_lum ; lum = coeff[0]
|| MV .L1X B_csr, A_csr ; Partitioning MV
STW .D1T1 A11, *+A_SP[ 6] ; Save A11
|| STW .D2T2 B11, *+B_SP[ 5] ; Save B11
;-
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