sdram.c

有关于USB的一些主机端驱动

/******************************************************************************
sdram.c

In this document, it descripts the functions for SDRAM access via DSP DMA

Chenyue, ChinaDigipro, 2002/11/21
******************************************************************************/

//#include "chen_mpeg_dec.h"
//#include "gsm.h"

/*-----------------------------------------------------------------------------
void SdramRead(	unsigned long src_addr, 
				unsigned long dst_addr, 
				short el_cnt, short fr_cnt, 
				short el_ind, short fr_ind)
-------------------------------------------------------------------------------
Description:				
	Data from SDRAM to DARAM, using DMA channel 0.
	burst mode: burst 16 byte
	source addressing mode: double index
	destination addressing mode: automatic post-incremented
	
Refernece document: 
	sdram.doc

Parameters:
	unsigned long src_addr: source address(SDRAM), WORD address
	unsigned long dst_addr: destination address(DARAM), WORD address
	short el_cnt: element's count per frame
	short fr_cnt: frame count per block
	short el_ind: for source, address offset after each elements transfer
	short fr_ind: for source, address offser after each frame transfer
-------------------------------------------------------------------------------
Chenyue, ChinaDigipro, 2002/11/21
-----------------------------------------------------------------------------*/
extern ioport int* ioport_pointer;

void SdramRead(unsigned long src_addr, unsigned long dst_addr, short el_cnt, short fr_cnt, short el_ind, short fr_ind)
{
	//source and destination address use BYTE address in DMA
	src_addr <<= 1; 
	dst_addr <<= 1;
	
	fr_ind = ((fr_ind-el_cnt)<<1)+1;
	
	//modify source and destination address registers
	ioport_pointer[0x0C04] = (unsigned short)(src_addr&0xFFFF);        //DMA_CSSA_L0
	ioport_pointer[0x0C05] = (unsigned short)((src_addr>>16)&0x00FF);  //DMA_CSSA_U0
	ioport_pointer[0x0C06] = (unsigned short)(dst_addr&0xFFFF);        //DMA_CDSA_L0
	ioport_pointer[0x0C07] = (unsigned short)((dst_addr>>16)&0x00FF);  //DMA_CDSA_U0
	
	//modify source frame and element count and index registers
	ioport_pointer[0x0C08] = el_cnt;  //DMA_CEN0
	ioport_pointer[0x0C09] = fr_cnt;  //DMA_CFN0
	ioport_pointer[0x0C0A] = fr_ind;  //DMA_CSFI0
	ioport_pointer[0x0C0B] = el_ind;  //DMA_CSEI0
	ioport_pointer[0x0C0E] = el_ind;  //DMA_CDEI0
	ioport_pointer[0x0C0F] = fr_ind;  //DMA_CDFI0          
	
	//modify Channel 0 source destination parameters register
	ioport_pointer[0x0C00] = 0xA349;
	//wait for last transfer finishing
	while(ioport_pointer[0x0C01]&0x0080); 
	
	
	//modify Channel 0 control register and start transfer
	ioport_pointer[0x0C01] = 0x78C0;
	while(ioport_pointer[0x0C01]&0x0080);

	return;
}


/*-----------------------------------------------------------------------------
void SdramWrite(unsigned long src_addr, 
				unsigned long dst_addr, 
				short el_cnt, short fr_cnt, 
				short el_ind, short fr_ind)
-------------------------------------------------------------------------------
Description:				
	Data from DARAM to SDRAM, using DMA channel 0.
	burst mode: burst 16 byte
	source addressing mode: automatic post-incremented
	destination addressing mode: double index
	
Refernece document: 
	sdram.doc

Parameters:
	unsigned long src_addr: source address(DARAM), WORD address
	unsigned long dst_addr: destination address(SDRAM), WORD address
	short el_cnt: element's count per frame
	short fr_cnt: frame count per block
	short el_ind: for destination, address offset after each elements transfer
	short fr_ind: for destination, address offser after each frame transfer
-------------------------------------------------------------------------------
Chenyue, ChinaDigipro, 2002/11/21
-----------------------------------------------------------------------------*/
void SdramWrite(unsigned long src_addr, unsigned long dst_addr, short el_cnt, short fr_cnt, short el_ind, short fr_ind, short channel)
{
	short reg;
	
	reg = 0x0C00 + (channel<<5);
	//source and destination address use BYTE address in DMA
	src_addr <<= 1;
	dst_addr <<= 1;

	fr_ind = ((fr_ind-el_cnt)<<1)+1;

	//modify source and destination address registers
	ioport_pointer[reg+4] = (unsigned short)(src_addr&0xFFFF);        //DMA_CSSA_L0
	ioport_pointer[reg+5] = (unsigned short)((src_addr>>16)&0x00FF);  //DMA_CSSA_U0
	ioport_pointer[reg+6] = (unsigned short)(dst_addr&0xFFFF);        //DMA_CDSA_L0
	ioport_pointer[reg+7] = (unsigned short)((dst_addr>>16)&0x00FF);  //DMA_CDSA_U0

	//modify source frame and element count and index registers
	ioport_pointer[reg+8] = el_cnt;  //DMA_CEN0
	ioport_pointer[reg+9] = fr_cnt;  //DMA_CFN0
	ioport_pointer[reg+10] = fr_ind;  //DMA_CSFI0
	ioport_pointer[reg+11] = el_ind;  //DMA_CSEI0
	ioport_pointer[reg+14] = el_ind;  //DMA_CDEI0
	ioport_pointer[reg+15] = fr_ind;  //DMA_CDFI0
	
	//modify Channel 0 source destination parameters register
	ioport_pointer[reg] = 0xA545;
	//wait for last transfer finishing
	while(ioport_pointer[reg+1]&0x0080);
	

	//modify Channel 0 control register and start transfer
	ioport_pointer[reg+1] = 0xD880;
//	while(ioport_pointer[0x0C01]&0x0080) idle_time++;
	
	return;
}


/*-----------------------------------------------------------------------------
void SdramWrite_noBurst(unsigned long src_addr, 
						unsigned long dst_addr, 
						short el_cnt, short fr_cnt, 
						short el_ind, short fr_ind)
-------------------------------------------------------------------------------
Description:				
	Data from DARAM to SDRAM, using DMA channel 0.
	burst mode: NO burst
	source addressing mode: automatic post-incremented
	destination addressing mode: double index
	
Refernece document: 
	sdram.doc

Parameters:
	unsigned long src_addr: source address(DARAM), WORD address
	unsigned long dst_addr: destination address(SDRAM), WORD address
	short el_cnt: element's count per frame
	short fr_cnt: frame count per block
	short el_ind: for destination, address offset after each elements transfer
	short fr_ind: for destination, address offser after each frame transfer
-------------------------------------------------------------------------------
Chenyue, ChinaDigipro, 2002/11/21
-----------------------------------------------------------------------------*/
void SdramWrite_noBurst(unsigned long src_addr, unsigned long dst_addr, short el_cnt, short fr_cnt, short el_ind, short fr_ind)
{
	//source and destination address use BYTE address in DMA
	src_addr <<= 1;
	dst_addr <<= 1;

	fr_ind = ((fr_ind-el_cnt)<<1)+1;

	//modify source and destination address registers
	ioport_pointer[0x0C04] = (unsigned short)(src_addr&0xFFFF);        //DMA_CSSA_L0
	ioport_pointer[0x0C05] = (unsigned short)((src_addr>>16)&0x00FF);  //DMA_CSSA_U0
	ioport_pointer[0x0C06] = (unsigned short)(dst_addr&0xFFFF);        //DMA_CDSA_L0
	ioport_pointer[0x0C07] = (unsigned short)((dst_addr>>16)&0x00FF);  //DMA_CDSA_U0

	//modify source frame and element count and index registers
	ioport_pointer[0x0C08] = el_cnt;  //DMA_CEN0
	ioport_pointer[0x0C09] = fr_cnt;  //DMA_CFN0
	ioport_pointer[0x0C0A] = fr_ind;  //DMA_CSFI0
	ioport_pointer[0x0C0B] = el_ind;  //DMA_CSEI0
	ioport_pointer[0x0C0E] = fr_ind;  //DMA_CDEI0
	ioport_pointer[0x0C0F] = el_ind;  //DMA_CDFI0
	
	//wait for last transfer finishing
	while(ioport_pointer[0x0C01]&0x0080); 
	
	//modify Channel 0 source destination parameters register
	ioport_pointer[0x0C00] = 0x0445;

	//modify Channel 0 control register and start transfer
	ioport_pointer[0x0C01] = 0xD8C0;
	while(ioport_pointer[0x0C01]&0x0080);
	
	return;
}

/*********************************** END *************************************/