omap30_dspintf_l3.c

有关于USB的一些主机端驱动

//-------------------------------------------------------------------------------
//            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
//                                                                             
//   Property of Texas Instruments 
//   For  Unrestricted  Internal  Use  Only 
//   Unauthorized reproduction and/or distribution is strictly prohibited.  
//   This product is protected under copyright law and trade secret law 
//   as an unpublished work.  
//   Created 2000, (C) Copyright 1999 Texas Instruments.  All rights reserved.
//
//-------------------------------------------------------------------------------
#include "omap30_l3.h"

//------------------------------------
//    MGSINT Array
//------------------------------------
UWORD16 MGSINT[NUM_OF_MGS_INT] = {

/* EMU_INT      */    DSPINT_INT2, 
/* EMIF_INT     */    DSPINT_INT16, 
/* INTH0_INT    */    DSPINT_INT3, 
/* INTH1_INT    */    DSPINT_INT11, 
/* RHEA_INT     */    DSPINT_INT19, 
/* TIMER1_INT   */    DSPINT_INT23, 
/* MAILBOX1_INT */    DSPINT_INT5, 
/* LOCALBUS_INT */    DSPINT_INT17, 
/* HSAB_INT     */    DSPINT_INT6, 
/* GPIO_INT     */    DSPINT_INT7, 
/* UART_INT     */    DSPINT_INT12, 
/* WDGTIMER_INT */    DSPINT_INT13, 
/* TC_ABORT_INT */    DSPINT_INT4, 
/* TIMER2_INT   */    DSPINT_INT22, 
/* TIMER3_INT   */    DSPINT_INT8, 
/* DMA_CH0_INT  */    DSPINT_INT18, 
/* DMA_CH1_INT  */    DSPINT_INT9, 
/* DMA_CH2_INT  */    DSPINT_INT20, 
/* DMA_CH3_INT  */    DSPINT_INT21, 
/* DMA_CH4_INT  */    DSPINT_INT14, 
/* DMA_CH5_INT  */    DSPINT_INT15, 
/* HOST_INT     */    DSPINT_INT10

};

//---------------------------------------------------------------------------
// NAME        : DSPINT_MoveIVT
// DESCRIPTION : Relocate Interrupt Vector Table to SARAM31
//
// PARAMETERS  : None
//
// RETURN VALUE: None
// LIMITATIONS : None
//---------------------------------------------------------------------------
void DSPINT_MoveIVT(void)
{
  // Modify the Interrupt Vector Pointer for the DSP vectors
  // to point to SARAM31
  SetGroupBits16(MEM16(IVPD_REG_ADDR), IVPD_POS, IVPD_NUMB,
  MEM_SARAM11_ADDRESS >> 8);
  
  // Modify the Interrupt Vector Pointer for the Host vectors
  // to point to SARAM31
  SetGroupBits16(MEM16(IVPH_REG_ADDR), IVPH_POS, IVPH_NUMB,
  MEM_SARAM11_ADDRESS >> 8);
}


//---------------------------------------------------------------------------
// NAME        : DSPINT_AddEntryToIVT
// DESCRIPTION : Add a new entry to the Interrupt Vector Table
//               (Interrupt Vector Table Located in SARAM31)
//
// PARAMETERS  :
//   MGSIntNum       = Number of the Megastar interrupt [0 .. 21] to be linked with
//                     the Interrupt Service Routine :
//                     EMU_INT, EMIF_INT, INTH0_INT, INTH1_INT, RHEA_INT,
//                     TIMER1_INT, MAILBOX1_INT, LOCALBUS_INT, HSAB_INT,
//                     GPIO_INT, UART_INT, WDGTIMER_INT, TC_ABORT_INT,
//                     TIMER2_INT, TIMER3_INT, DMA_CH0_INT, DMA_CH1_INT,
//                     DMA_CH2_INT, DMA_CH3_INT, DMA_CH4_INT, DMA_CH5_INT,
//                     HOST_INT
//   ISRAddr         = Address of the corresponding Interrupt Service Routine
//
// RETURN VALUE: None
// LIMITATIONS : None
//---------------------------------------------------------------------------
void DSPINT_AddEntryToIVT(UWORD16 MGSIntNum, UWORD32 ISRAddr)
{
UWORD32 InterruptVectorAddr;

  if (MGSIntNum <= 21)
  {
    // Compute address of Interrupt Vector Table entry (in word)
    InterruptVectorAddr = (MEM_SARAM11_ADDRESS + (MGSINT[MGSIntNum] << 3)) >> 1;
//    InterruptVectorAddr = 0xffff00 + (MGSINT[MGSIntNum] << 3);

    // Write the Branch instruction and 2 NOP_16 
    // at the Interrupt Vector Table Entry location
    // (far_poke : write to extended memory address)
    far_poke_l(InterruptVectorAddr, (UWORD32)B_P24_OPCODE << 24 | ISRAddr);    
    far_poke(InterruptVectorAddr + 2, NOP_16_OPCODE);
    far_poke(InterruptVectorAddr + 3, NOP_16_OPCODE);
  }
}


//---------------------------------------------------------------------------
// NAME        : DSPINT_EnableOneIT
// DESCRIPTION : Unmask one Megastar interrupt
//
// PARAMETERS  :
//   MGSIntNum       = Number of the Megastar Interrupt to be 
//                     unmasked [0 .. 21] :
//                     EMU_INT, EMIF_INT, INTH0_INT, INTH1_INT, RHEA_INT,
//                     TIMER1_INT, MAILBOX1_INT, LOCALBUS_INT, HSAB_INT,
//                     GPIO_INT, UART_INT, WDGTIMER_INT, TC_ABORT_INT,
//                     TIMER2_INT, TIMER3_INT, DMA_CH0_INT, DMA_CH1_INT,
//                     DMA_CH2_INT, DMA_CH3_INT, DMA_CH4_INT, DMA_CH5_INT,
//                     HOST_INT
//
// RETURN VALUE: None
// LIMITATIONS : None
//---------------------------------------------------------------------------
void DSPINT_EnableOneIT(UWORD16 MGSIntNum)
{
  if (MGSIntNum <= 21)
  {
    if (MGSINT[MGSIntNum] <= 15)
      SetBitIndex(MEM16(IER0_REG_ADDR), MGSINT[MGSIntNum]);
    else
      SetBitIndex(MEM16(IER1_REG_ADDR), (MGSINT[MGSIntNum] - 16));
  }
}


//---------------------------------------------------------------------------
// NAME        : DSPINT_DisableOneIT
// DESCRIPTION : Mask one Megastar interrupt
//
// PARAMETERS  :
//   MGSIntNum       = Number of the Megastar Interrupt to be 
//                     masked [0 .. 21] :
//                     EMU_INT, EMIF_INT, INTH0_INT, INTH1_INT, RHEA_INT,
//                     TIMER1_INT, MAILBOX1_INT, LOCALBUS_INT, HSAB_INT,
//                     GPIO_INT, UART_INT, WDGTIMER_INT, TC_ABORT_INT,
//                     TIMER2_INT, TIMER3_INT, DMA_CH0_INT, DMA_CH1_INT,
//                     DMA_CH2_INT, DMA_CH3_INT, DMA_CH4_INT, DMA_CH5_INT,
//                     HOST_INT
//
// RETURN VALUE: None
// LIMITATIONS : None
//---------------------------------------------------------------------------
void DSPINT_DisableOneIT(UWORD16 MGSIntNum)
{
  if (MGSIntNum <= 21)
  {
    if (MGSINT[MGSIntNum] <= 15)
      ClearBitIndex(MEM16(IER0_REG_ADDR), MGSINT[MGSIntNum]);
    else
      ClearBitIndex(MEM16(IER1_REG_ADDR), (MGSINT[MGSIntNum] - 16));
  }
}


//---------------------------------------------------------------------------
// NAME        : DSPINT_EnableAllIT
// DESCRIPTION : Unmask all interrupts
//
// PARAMETERS  : None
//
// RETURN VALUE: None
// LIMITATIONS : None
//---------------------------------------------------------------------------
void DSPINT_EnableAllIT(void)
{
  SetBit(MEM16(IER0_REG_ADDR), IER0_ALLINT_MASK);
  SetBit(MEM16(IER1_REG_ADDR), IER1_ALLINT_MASK);
}


//---------------------------------------------------------------------------
// NAME        : DSPINT_DisableAllIT
// DESCRIPTION : Mask all interrupts
//
// PARAMETERS  : None
//
// RETURN VALUE: None
// LIMITATIONS : None
//---------------------------------------------------------------------------
void DSPINT_DisableAllIT(void)
{
  ClearBit(MEM16(IER0_REG_ADDR), IER0_ALLINT_MASK);
  ClearBit(MEM16(IER1_REG_ADDR), IER1_ALLINT_MASK);
}


//---------------------------------------------------------------------------
// NAME        : DSPINT_EnableGlobalIT
// DESCRIPTION : Enable the maskable interrupts
//
// PARAMETERS  : None
//
// RETURN VALUE: None
// LIMITATIONS : None
//---------------------------------------------------------------------------
void DSPINT_EnableGlobalIT(void)
{
//  ClearBitIndex(MEM16(ST1_REG_ADDR), ST1_INTM_POS);
  asm("	bit(ST1,#ST1_INTM) = #0");
//  asm("	MOV #11,T0");
//  asm("	MOV #03,AR0");
//  asm("	BCLR T0,*AR0");
}


//---------------------------------------------------------------------------
// NAME        : DSPINT_DisableGlobalIT
// DESCRIPTION : Disable the maskable interrupts
//
// PARAMETERS  : None
//
// RETURN VALUE: None
// LIMITATIONS : None
//---------------------------------------------------------------------------
void DSPINT_DisableGlobalIT(void)
{
//  SetBitIndex(MEM16(ST1_REG_ADDR), ST1_INTM_POS);
  asm("	bit(ST1,#ST1_INTM) = #1");
//  asm("	MOV #11,T0");
//  asm("	MOV #03,AR0");
//  asm("	BSET T0,*AR0");
}


//---------------------------------------------------------------------------
// NAME        : DSPINT_GetPendingIT
// DESCRIPTION : Return the pending interrupts (IFR0 and IFR1)
//
// PARAMETERS  : None
//
// RETURN VALUE: Return value of Interrupt Flag Registers
// LIMITATIONS : None
//---------------------------------------------------------------------------
UWORD32 DSPINT_GetPendingIT(void)
{
   return(((UWORD32) MEM16(IFR1_REG_ADDR) << 16) || MEM16(IFR0_REG_ADDR));
}


//---------------------------------------------------------------------------
// NAME        : DSPINT_MapMGSINT
// DESCRIPTION : Map a Megastar interrupt to one of the 22 maskable interrupt
//
// PARAMETERS  :
//   DSPIntNum       = Number of Maskable Interrupt [2 .. 23] :
//                     DSPINT_INTn (n = {2 .. 23})
//   MGSIntNum       = Number of the Megastar Interrupt [0 .. 21] :
//                     EMU_INT, EMIF_INT, INTH0_INT, INTH1_INT, RHEA_INT,
//                     TIMER1_INT, MAILBOX1_INT, LOCALBUS_INT, HSAB_INT,
//                     GPIO_INT, UART_INT, WDGTIMER_INT, TC_ABORT_INT,
//                     TIMER2_INT, TIMER3_INT, DMA_CH0_INT, DMA_CH1_INT,
//                     DMA_CH2_INT, DMA_CH3_INT, DMA_CH4_INT, DMA_CH5_INT,
//                     HOST_INT
//
// RETURN VALUE: If correct return TRUE, otherwise FALSE
// LIMITATIONS : None
//---------------------------------------------------------------------------
UWORD16 DSPINT_MapMGSINT(UWORD16 DSPIntNum, 
                         UWORD16 MGSIntNum)
{
UWORD32 RegAddr;
UWORD16 Position = PER_PIN0_POS;

  switch (DSPIntNum)
  {
    case 2 : // PER1
    case 3 :
    {
      RegAddr = RHEA_PER1_REG_ADDR;
      if (DSPIntNum != 2)
        Position = PER_PIN1_POS;
      break;
    }
    
    case 4 : // PER2
    case 5 :
    {
      RegAddr = RHEA_PER2_REG_ADDR;
      if (DSPIntNum != 4)
        Position = PER_PIN1_POS;
      break;
    }
    
    case 6 : // PER3
    case 7 :
    {
      RegAddr = RHEA_PER3_REG_ADDR;
      if (DSPIntNum != 6)
        Position = PER_PIN1_POS;
      break;
    }
    
    case 8 : // PER4
    case 9 :
    {
      RegAddr = RHEA_PER4_REG_ADDR;
      if (DSPIntNum != 8)
        Position = PER_PIN1_POS;
      break;
    }
    
    case 10 : // PER5
    case 11 :
    {
      RegAddr = RHEA_PER5_REG_ADDR;
      if (DSPIntNum != 10)
        Position = PER_PIN1_POS;
      break;
    }
    
    case 12 : // PER6
    case 13 :
    {
      RegAddr = RHEA_PER6_REG_ADDR;
      if (DSPIntNum != 12)
        Position = PER_PIN1_POS;
      break;
    }
    
    case 14 : // PER7
    case 15 :
    {
      RegAddr = RHEA_PER7_REG_ADDR;
      if (DSPIntNum != 14)
        Position = PER_PIN1_POS;
      break;
    }
    
    case 16 : // PER8
    case 17 :
    {
      RegAddr = RHEA_PER8_REG_ADDR;
      if (DSPIntNum != 16)
        Position = PER_PIN1_POS;
      break;
    }
    
    case 18 : // PER9
    case 19 :
    {
      RegAddr = RHEA_PER9_REG_ADDR;
      if (DSPIntNum != 18)
        Position = PER_PIN1_POS;
      break;
    }
    
    case 20 : // PER10
    case 21 :
    {
      RegAddr = RHEA_PER10_REG_ADDR;
      if (DSPIntNum != 20)
        Position = PER_PIN1_POS;
      break;
    }
    
    case 22 : // PER11
    case 23 :
    {
      RegAddr = RHEA_PER11_REG_ADDR;
      if (DSPIntNum != 22)
        Position = PER_PIN1_POS;
      break;
    }
    
    default :
    {
      return(FALSE);
    }
  }
  
  // Modify settings in Priority Encoder Register (PER Register)
  SetGroupBits16(MEM16(RegAddr), Position, PER_PIN_NUMB, MGSIntNum);
  // Modify the corresponding entry in MGSINT array
  MGSINT[MGSIntNum] = DSPIntNum;
  
  return(TRUE);
}