📄 omap30_l3.h
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//-------------------------------------------------------------------------------
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
//
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work.
// Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved.
//
//-------------------------------------------------------------------------------
#ifndef _MEM_L3__HH
#define _MEM_L3__HH
//-------------------------------------------------------------------------------
//
// COMMON LIBRARY INCLUDES
//
//-------------------------------------------------------------------------------
#include "global_types_l3.h"
#include "omap30_dspclkrst_l3.h"
#include "omap30_dspintf_l3.h"
#include "omap30_dspmbx_l3.h"
//#include "mgs3_rhea_l3.h"
#include "omap30_system_init_l3.h"
#include "omap30_dspwdg_l3.h"
#include "omap30_dsptimer_l3.h"
//-------------------------------------------------------------------------------
//
// COMMON FUNCTIONNAL DEFINES
//
//-------------------------------------------------------------------------------
// Opcode of B P24 instruction
#define B_P24_OPCODE 0x6A
// Opcode of NOP_16 instruction
#define NOP_16_OPCODE 0x5E80
//-------------------------------------------------------------------------------
//
// MEGASTAR3 EXTERNAL MEMORY MAPPING (Byte address)
//
//-------------------------------------------------------------------------------
// CE0 Memory Space
#define MEM_EXTERN0_ADDRESS 0x00050000
#define MEM_EXTERN0_LENGTH 0x003B0000
// CE1 Memory Space
#define MEM_EXTERN1_ADDRESS 0x00400000
#define MEM_EXTERN1_LENGTH 0x00400000
// CE2 Memory Space
#define MEM_EXTERN2_ADDRESS 0x00800000
#define MEM_EXTERN2_LENGTH 0x00400000
// CE3 Memory Space
#define MEM_EXTERN3_ADDRESS 0x00C00000
#define MEM_EXTERN3_LENGTH 0x003F8000
//-------------------------------------------------------------------------------
//
// MEGASTAR3 INTERNAL MEMORY MAPPING
//
//-------------------------------------------------------------------------------
#define MEM_MMR_ADDRESS 0x00000000
#define MEM_MMR_LENGTH 0x00000100
#define MEM_DARAM0_ADDRESS 0x00000100
#define MEM_DARAM0_LENGTH 0x00001F00
#define MEM_DARAM1_ADDRESS 0x00002000
#define MEM_DARAM1_LENGTH 0x00002000
#define MEM_DARAM2_ADDRESS 0x00004000
#define MEM_DARAM2_LENGTH 0x00002000
#define MEM_DARAM3_ADDRESS 0x00006000
#define MEM_DARAM3_LENGTH 0x00002000
#define MEM_DARAM4_ADDRESS 0x00008000
#define MEM_DARAM4_LENGTH 0x00002000
#define MEM_DARAM5_ADDRESS 0x0000A000
#define MEM_DARAM5_LENGTH 0x00002000
#define MEM_DARAM6_ADDRESS 0x0000C000
#define MEM_DARAM6_LENGTH 0x00002000
#define MEM_DARAM7_ADDRESS 0x0000E000
#define MEM_DARAM7_LENGTH 0x00002000
#define MEM_SARAM0_ADDRESS 0x00010000
#define MEM_SARAM0_LENGTH 0x00002000
#define MEM_SARAM1_ADDRESS 0x00012000
#define MEM_SARAM1_LENGTH 0x00002000
#define MEM_SARAM2_ADDRESS 0x00014000
#define MEM_SARAM2_LENGTH 0x00002000
#define MEM_SARAM3_ADDRESS 0x00016000
#define MEM_SARAM3_LENGTH 0x00002000
#define MEM_SARAM4_ADDRESS 0x00018000
#define MEM_SARAM4_LENGTH 0x00002000
#define MEM_SARAM5_ADDRESS 0x0001A000
#define MEM_SARAM5_LENGTH 0x00002000
#define MEM_SARAM6_ADDRESS 0x0001C000
#define MEM_SARAM6_LENGTH 0x00002000
#define MEM_SARAM7_ADDRESS 0x0001E000
#define MEM_SARAM7_LENGTH 0x00002000
#define MEM_SARAM8_ADDRESS 0x00020000
#define MEM_SARAM8_LENGTH 0x00002000
#define MEM_SARAM9_ADDRESS 0x00022000
#define MEM_SARAM9_LENGTH 0x00002000
#define MEM_SARAM10_ADDRESS 0x00024000
#define MEM_SARAM10_LENGTH 0x00002000
#define MEM_SARAM11_ADDRESS 0x00026000
#define MEM_SARAM11_LENGTH 0x00002000
#define MEM_SARAM12_ADDRESS 0x00028000
#define MEM_SARAM12_LENGTH 0x00002000
#define MEM_SARAM13_ADDRESS 0x0002A000
#define MEM_SARAM13_LENGTH 0x00002000
#define MEM_SARAM14_ADDRESS 0x0002C000
#define MEM_SARAM14_LENGTH 0x00002000
#define MEM_SARAM15_ADDRESS 0x0002E000
#define MEM_SARAM15_LENGTH 0x00002000
#define MEM_SARAM16_ADDRESS 0x00030000
#define MEM_SARAM16_LENGTH 0x00002000
#define MEM_SARAM17_ADDRESS 0x00032000
#define MEM_SARAM17_LENGTH 0x00002000
#define MEM_SARAM18_ADDRESS 0x00034000
#define MEM_SARAM18_LENGTH 0x00002000
#define MEM_SARAM19_ADDRESS 0x00036000
#define MEM_SARAM19_LENGTH 0x00002000
#define MEM_SARAM20_ADDRESS 0x00038000
#define MEM_SARAM20_LENGTH 0x00002000
#define MEM_SARAM21_ADDRESS 0x0003A000
#define MEM_SARAM21_LENGTH 0x00002000
#define MEM_SARAM22_ADDRESS 0x0003C000
#define MEM_SARAM22_LENGTH 0x00002000
#define MEM_SARAM23_ADDRESS 0x0003E000
#define MEM_SARAM23_LENGTH 0x00002000
#define MEM_SARAM24_ADDRESS 0x00040000
#define MEM_SARAM24_LENGTH 0x00002000
#define MEM_SARAM25_ADDRESS 0x00042000
#define MEM_SARAM25_LENGTH 0x00002000
#define MEM_SARAM26_ADDRESS 0x00044000
#define MEM_SARAM26_LENGTH 0x00002000
#define MEM_SARAM27_ADDRESS 0x00046000
#define MEM_SARAM27_LENGTH 0x00002000
#define MEM_SARAM28_ADDRESS 0x00048000
#define MEM_SARAM28_LENGTH 0x00002000
#define MEM_SARAM29_ADDRESS 0x0004A000
#define MEM_SARAM29_LENGTH 0x00002000
#define MEM_SARAM30_ADDRESS 0x0004C000
#define MEM_SARAM30_LENGTH 0x00002000
#define MEM_SARAM31_ADDRESS 0x0004E000
#define MEM_SARAM31_LENGTH 0x00002000
#define MEM_PDROM_ADDRESS 0x00FF8000
#define MEM_PDROM_LENGTH 0x00007E00
#define MEM_DATAROM_ADDRESS 0x00FFFE00
#define MEM_DATAROM_LENGTH 0x00000100
#define MEM_INTVEC_ADDRESS 0x00FFFF00
#define MEM_INTVEC_LENGTH 0x00000100
// Lead3 Memory Mapped Registers (Control and Status reg only )
// (word addresses)
#define IER0_REG_ADDR 0x00
#define IFR0_REG_ADDR 0x01
#define ST0_REG_ADDR 0x02
#define ST1_REG_ADDR 0x03
#define ST3_REG_ADDR 0x04
#define IER1_REG_ADDR 0x45
#define IFR1_REG_ADDR 0x46
#define DBIER0_REG_ADDR 0x47
#define DBIER1_REG_ADDR 0x48
#define IVPD_REG_ADDR 0x49
#define IVPH_REG_ADDR 0x4A
#define ST2_REG_ADDR 0x4B
// Mapping of Configuration Registers (I/O Space) (word addresses)
#define BASE_ADDR_RHEA_STROBE1 0x00000000
#define BASE_ADDR_RHEA_STROBE2 0x00008000
#define OFFSET_IN_WORD 0x400 // 1 KWord
#define IO_RHEA_ADDR (BASE_ADDR_RHEA_STROBE1)
#define IO_ETM_ADDR (BASE_ADDR_RHEA_STROBE1+ 1*OFFSET_IN_WORD)
#define IO_EMIF_ADDR (BASE_ADDR_RHEA_STROBE1+ 2*OFFSET_IN_WORD)
#define IO_DMA_ADDR (BASE_ADDR_RHEA_STROBE1+ 3*OFFSET_IN_WORD)
#define IO_ICACHE_ADDR (BASE_ADDR_RHEA_STROBE1+ 5*OFFSET_IN_WORD)
#define IO_TRACE_ADDR (BASE_ADDR_RHEA_STROBE1+ 8*OFFSET_IN_WORD)
#define IO_TIMER1_ADDR (BASE_ADDR_RHEA_STROBE1+10*OFFSET_IN_WORD)
#define IO_TIMER2_ADDR (BASE_ADDR_RHEA_STROBE1+11*OFFSET_IN_WORD)
#define IO_TIMER3_ADDR (BASE_ADDR_RHEA_STROBE1+12*OFFSET_IN_WORD)
#define IO_WDGTIMER_ADDR (BASE_ADDR_RHEA_STROBE1+13*OFFSET_IN_WORD)
#define IO_DSPINT_IF_ADDR (BASE_ADDR_RHEA_STROBE1+14*OFFSET_IN_WORD)
#define IO_CLKRST_ADDR (BASE_ADDR_RHEA_STROBE1+16*OFFSET_IN_WORD)
#define IO_INTH_ADDR (BASE_ADDR_RHEA_STROBE1+18*OFFSET_IN_WORD)
#define IO_GPIO_ADDR (BASE_ADDR_RHEA_STROBE2+28*OFFSET_IN_WORD)
#define IO_UART_ADDR (BASE_ADDR_RHEA_STROBE2+29*OFFSET_IN_WORD)
#define IO_MAILBOX_ADDR (BASE_ADDR_RHEA_STROBE2+30*OFFSET_IN_WORD)
//-------------------------------------------------------------------------------
//
// OMAP3.0 INTERRUPT MAPPING
//
//-------------------------------------------------------------------------------
extern UWORD16 MGSINT[NUM_OF_MGS_INT]; //define in the main of the program
#endif
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