📄 omap30_dspclkrst_l3.h
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//-------------------------------------------------------------------------------
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
//
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work.
// Created 2000, (C) Copyright 1999 Texas Instruments. All rights reserved.
//
//-------------------------------------------------------------------------------
#ifndef _DSPCLKRST__H
#define _DSPCLKRST__H
//-------------------------------------------------------------------------------
//
// DSP REGISTERS DECLARATION
//
//-------------------------------------------------------------------------------
#define DSPCLKRST_BASE_ADDR IO_CLKRST_ADDR
//Register Offset
//-------------------
#define DSPCLKRST_DSP_CKTL_OFFSET 0x00
#define DSPCLKRST_DSP_IDLECT1_OFFSET 0x04
#define DSPCLKRST_DSP_IDLECT2_OFFSET 0x08
#define DSPCLKRST_DSP_EWUPCT_OFFSET 0x0C
#define DSPCLKRST_DSP_RSTCT1_OFFSET 0x10
#define DSPCLKRST_DSP_RSTCT2_OFFSET 0x14
#define DSPCLKRST_DSP_SYSST_OFFSET 0x18
#define DSPCLKRST_DSP_CKOUT1_OFFSET 0x1C
#define DSPCLKRST_DSP_CKOUT2_OFFSET 0x20
//DSPCLKRST_DSP_CKTL
//-------------------
#define DSPCLKRST_DSP_CKTL REG16(DSPCLKRST_BASE_ADDR+DSPCLKRST_DSP_CKTL_OFFSET)
#define DSPCLKRST_DSP_CKTL_RESERVED_POS 9
#define DSPCLKRST_DSP_CKTL_RESERVED_NUMB 7
#define DSPCLKRST_DSP_CKTL_RESERVED_RES_VAL 0x00
//R/W
#define DSPCLKRST_DSP_CKTL_TIMXO_POS 8
#define DSPCLKRST_DSP_CKTL_TIMXO_NUMB 1
#define DSPCLKRST_DSP_CKTL_TIMXO_RES_VAL 0x1
//R/W
#define DSPCLKRST_DSP_CKTL_GPIOXO_POS 7
#define DSPCLKRST_DSP_CKTL_GPIOXO_NUMB 1
#define DSPCLKRST_DSP_CKTL_GPIOXO_RES_VAL 0x1
//R/W
#define DSPCLKRST_DSP_CKTL_GPIODIV_POS 5
#define DSPCLKRST_DSP_CKTL_GPIODIV_NUMB 2
#define DSPCLKRST_DSP_CKTL_GPIODIV_RES_VAL 0x0
//R/W
#define DSPCLKRST_DSP_CKTL_UARTXO_POS 4
#define DSPCLKRST_DSP_CKTL_UARTXO_NUMB 1
#define DSPCLKRST_DSP_CKTL_UARTXO_RES_VAL 0x1
//R/W
#define DSPCLKRST_DSP_CKTL_UARTDIV_POS 2
#define DSPCLKRST_DSP_CKTL_UARTDIV_NUMB 2
#define DSPCLKRST_DSP_CKTL_UARTDIV_RES_VAL 0x0
//R/W
#define DSPCLKRST_DSP_CKTL_PERDIV_POS 0
#define DSPCLKRST_DSP_CKTL_PERDIV_NUMB 2
#define DSPCLKRST_DSP_CKTL_PERDIV_RES_VAL 0X0
//R/W
//DSPCLKRST_DSP_IDLECT1
//-------------------
#define DSPCLKRST_DSP_IDLECT1 REG16(DSPCLKRST_BASE_ADDR+DSPCLKRST_DSP_IDLECT1_OFFSET)
#define DSPCLKRST_DSP_IDLECT1_RESERVED_POS 9
#define DSPCLKRST_DSP_IDLECT1_RESERVED_NUMB 7
#define DSPCLKRST_DSP_IDLECT1_RESERVED_RES_VAL 0x0
//R/W
#define DSPCLKRST_DSP_IDLECT1_IDLTIM_DSP_POS 8
#define DSPCLKRST_DSP_IDLECT1_IDLTIM_DSP_NUMB 1
#define DSPCLKRST_DSP_IDLECT1_IDLTIM_DSP_RES_VAL 0x0
//R/W
#define DSPCLKRST_DSP_IDLECT1_IDLGPIO_DSP_POS 7
#define DSPCLKRST_DSP_IDLECT1_IDLGPIO_DSP_NUMB 1
#define DSPCLKRST_DSP_IDLECT1_IDLGPIO_DSP_RES_VAL 0x0
//R/W
#define DSPCLKRST_DSP_IDLECT1_WKUP_MODE_POS 6
#define DSPCLKRST_DSP_IDLECT1_WKUP_MODE_NUMB 1
#define DSPCLKRST_DSP_IDLECT1_WKUP_MODE_RES_VAL 0x1
//R/W
#define DSPCLKRST_DSP_IDLECT1_IDLDPLL_DSP_POS 5
#define DSPCLKRST_DSP_IDLECT1_IDLDPLL_DSP_NUMB 1
#define DSPCLKRST_DSP_IDLECT1_IDLDPLL_DSP_RES_VAL 0x0
//R/W
#define DSPCLKRST_DSP_IDLECT1_IDLIF_DSP_POS 4
#define DSPCLKRST_DSP_IDLECT1_IDLIF_DSP_NUMB 1
#define DSPCLKRST_DSP_IDLECT1_IDLIF_DSP_RES_VAL 0x0
//R/W
#define DSPCLKRST_DSP_IDLECT1_IDLUART_DSP_POS 3
#define DSPCLKRST_DSP_IDLECT1_IDLUART_DSP_NUMB 1
#define DSPCLKRST_DSP_IDLECT1_IDLUART_DSP_RES_VAL 0x0
//R/W
#define DSPCLKRST_DSP_IDLECT1_IDLPER_DSP_POS 2
#define DSPCLKRST_DSP_IDLECT1_IDLPER_DSP_NUMB 1
#define DSPCLKRST_DSP_IDLECT1_IDLPER_DSP_RES_VAL 0x0
//R/W
#define DSPCLKRST_DSP_IDLECT1_IDLXORP_DSP_POS 1
#define DSPCLKRST_DSP_IDLECT1_IDLXORP_DSP_NUMB 1
#define DSPCLKRST_DSP_IDLECT1_IDLXORP_DSP_RES_VAL 0x0
//R/W
#define DSPCLKRST_DSP_IDLECT1_IDLWDT_DSP_POS 0
#define DSPCLKRST_DSP_IDLECT1_IDLWDT_DSP_NUMB 1
#define DSPCLKRST_DSP_IDLECT1_IDLWDT_DSP_RES_VAL 0x0
//R/W
//DSPCLKRST_DSP_IDLECT2
//-------------------
#define DSPCLKRST_DSP_IDLECT2 REG16(DSPCLKRST_BASE_ADDR+DSPCLKRST_DSP_IDLECT2_OFFSET)
#define DSPCLKRST_DSP_IDLECT2_RESERVED_POS 6
#define DSPCLKRST_DSP_IDLECT2_RESERVED_NUMB 10
#define DSPCLKRST_DSP_IDLECT2_RESERVED_RES_VAL 0x0
//R/W
#define DSPCLKRST_DSP_IDLECT2_EN_TIMCK_POS 5
#define DSPCLKRST_DSP_IDLECT2_EN_TIMCK_NUMB 1
#define DSPCLKRST_DSP_IDLECT2_EN_TIMCK_RES_VAL 0x0
//R/W
#define DSPCLKRST_DSP_IDLECT2_EN_GPIOCK_POS 4
#define DSPCLKRST_DSP_IDLECT2_EN_GPIOCK_NUMB 1
#define DSPCLKRST_DSP_IDLECT2_EN_GPIOCK_RES_VAL 0x0
//R/W
#define DSPCLKRST_DSP_IDLECT2_EN_UARTCK_POS 3
#define DSPCLKRST_DSP_IDLECT2_EN_UARTCK_NUMB 1
#define DSPCLKRST_DSP_IDLECT2_EN_UARTCK_RES_VAL 0x0
//R/W
#define DSPCLKRST_DSP_IDLECT2_EN_PERCK_POS 2
#define DSPCLKRST_DSP_IDLECT2_EN_PERCK_NUMB 1
#define DSPCLKRST_DSP_IDLECT2_EN_PERCK_RES_VAL 0x0
//R/W
#define DSPCLKRST_DSP_IDLECT2_EN_XORPCK_POS 1
#define DSPCLKRST_DSP_IDLECT2_EN_XORPCK_NUMB 1
#define DSPCLKRST_DSP_IDLECT2_EN_XORPCK_RES_VAL 0x0
//R/W
#define DSPCLKRST_DSP_IDLECT2_EN_WDTCK_POS 0
#define DSPCLKRST_DSP_IDLECT2_EN_WDTCK_NUMB 1
#define DSPCLKRST_DSP_IDLECT2_EN_WDTCK_RES_VAL 0x0
//R/W
//DSPCLKRST_DSP_EWUPCT
//-------------------
#define DSPCLKRST_DSP_EWUPCT REG16(DSPCLKRST_BASE_ADDR+DSPCLKRST_DSP_EWUPCT_OFFSET)
#define DSPCLKRST_DSP_EWUPCT_RESERVED_POS 0
#define DSPCLKRST_DSP_EWUPCT_RESERVED_NUMB 16
#define DSPCLKRST_DSP_EWUPCT_RESERVED_RES_VAL 0x0
//R/W
//DSPCLKRST_DSP_RSTCT1
//-------------------
#define DSPCLKRST_DSP_RSTCT1 REG16(DSPCLKRST_BASE_ADDR+DSPCLKRST_DSP_RSTCT1_OFFSET)
#define DSPCLKRST_DSP_RSTCT1_RESERVED_POS 0
#define DSPCLKRST_DSP_RSTCT1_RESERVED_NUMB 16
#define DSPCLKRST_DSP_RSTCT1_RESERVED_RES_VAL 0x0
//R/W
//DSPCLKRST_DSP_RSTCT2
//-------------------
#define DSPCLKRST_DSP_RSTCT2 REG16(DSPCLKRST_BASE_ADDR+DSPCLKRST_DSP_RSTCT2_OFFSET)
#define DSPCLKRST_DSP_RSTCT2_RESERVED_POS 1
#define DSPCLKRST_DSP_RSTCT2_RESERVED_NUMB 15
#define DSPCLKRST_DSP_RSTCT2_RESERVED_RES_VAL 0x0
//R/W
#define DSPCLKRST_DSP_RSTCT2_PER_EN_POS 0
#define DSPCLKRST_DSP_RSTCT2_PER_EN_NUMB 1
#define DSPCLKRST_DSP_RSTCT2_PER_EN_RES_VAL 0x0
//R/W
//DSPCLKRST_DSP_SYSST
//-------------------
#define DSPCLKRST_DSP_SYSST REG16(DSPCLKRST_BASE_ADDR+DSPCLKRST_DSP_SYSST_OFFSET)
#define DSPCLKRST_DSP_SYSST_RESERVED_POS 14
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