📄 omap1510_inth2.h
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//===============================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
//
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work.
// Created 2000, (C) Copyright 1999 Texas Instruments. All rights reserved.
//
// Filename : inth2.h
//===============================================================================
#ifndef _OMAP1510_INTH2__H_
#define _OMAP1510_INTH2__H_
#define INTH_MASK_IT 1
#define INTH_UNMASK_IT 0
#define IT_DETECTED 1
#define IT_NOT_DETECTED 0
//##################################################################
// OFFSET OF THE 32 bits REGISTERS
//##################################################################
//-------------------------------------------------------------------------------
//
// ARM REGISTERS DECLARATION
//
//-------------------------------------------------------------------------------
#define LEV2_INTH_BASE_ADDR MEM_ARM_LEV2_INTH_ADDR
#define LEV2_INTH_IT_REG_OFFSET ARMINTH_IT_REG_OFFSET /* Interrupt register offset */
#define LEV2_INTH_MASK_IT_REG_OFFSET ARMINTH_MASK_IT_REG_OFFSET /* Mask Interrupt register offset */
#define LEV2_INTH_SOURCE_IRQ_REG_OFFSET ARMINTH_SOURCE_IRQ_REG_OFFSET /* Srce Binary coded IRQ register offset */
#define LEV2_INTH_SOURCE_FIQ_REG_OFFSET ARMINTH_SOURCE_FIQ_REG_OFFSET /* Srce Binary coded FIQ register offset */
#define LEV2_INTH_SOURCE_BIN_IRQ_REG_OFFSET ARMINTH_SOURCE_BIN_IRQ_REG_OFFSET /* Srce Binary coded IRQ register offset */
#define LEV2_INTH_SOURCE_BIN_FIQ_REG_OFFSET ARMINTH_SOURCE_BIN_FIQ_REG_OFFSET /* Srce Binary coded FIQ register offset */
#define LEV2_INTH_CTRL_REG_OFFSET ARMINTH_CTRL_REG_OFFSET /* Control register offset */
#define LEV2_INTH_IT_LEVEL_REG_OFFSET ARMINTH_IT_LEVEL_REG_OFFSET /* Interrupt Level registers offset */
#define LEV2_INTH_SISR_REG_OFFSET ARMINTH_SISR_REG_OFFSET /* Software Interrupt Set Register offset */
//ARMINTH_ITR
//-------------------
#define LEV2_INTH_ITR REG32(LEV2_INTH_BASE_ADDR + LEV2_INTH_IT_REG_OFFSET)
#define LEV2_INTH_ITR_REG (LEV2_INTH_BASE_ADDR + LEV2_INTH_IT_REG_OFFSET)
#define LEV2_INTH_ITR_ACT_IRQ_POS 0
#define LEV2_INTH_ITR_ACT_IRQ_NUMB 32
#define LEV2_INTH_ITR_ACT_IRQ_RES_VAL 0x0000
//R/W
//ARMINTH_MIR
//-------------------
#define LEV2_INTH_MIR REG32(LEV2_INTH_BASE_ADDR + LEV2_INTH_MASK_IT_REG_OFFSET)
#define LEV2_INTH_MIR_REG (LEV2_INTH_BASE_ADDR + LEV2_INTH_MASK_IT_REG_OFFSET)
#define LEV2_INTH_MIR_IRQ_MSK_POS 0
#define LEV2_INTH_MIR_IRQ_MSK_NUMB 32
#define LEV2_INTH_MIR_IRQ_MSK_RES_VAL 0xFFFF
//R/W
//ARMINTH_SIR_IRQ_CODE
//-------------------
#define LEV2_INTH_SIR_IRQ_CODE REG32(LEV2_INTH_BASE_ADDR + LEV2_INTH_SOURCE_BIN_IRQ_REG_OFFSET)
#define LEV2_INTH_SIR_IRQ_CODE_REG (LEV2_INTH_BASE_ADDR + LEV2_INTH_SOURCE_BIN_IRQ_REG_OFFSET)
#define LEV2_INTH_SIR_IRQ_CODE_IRQ_NUM_POS 0
#define LEV2_INTH_SIR_IRQ_CODE_IRQ_NUM_NUMB 5
#define LEV2_INTH_SIR_IRQ_CODE_IRQ_NUM_RES_VAL 0x0
#define LEV2_INTH_SIR_IRQ_CODE_IRQ_NUM_MASK 0x1F
//R
//ARMINTH_SIR_FIQ_CODE
//-------------------
#define LEV2_INTH_SIR_FIQ_CODE REG32(LEV2_INTH_BASE_ADDR + LEV2_INTH_SOURCE_BIN_FIQ_REG_OFFSET)
#define LEV2_INTH_SIR_FIQ_CODE_REG (LEV2_INTH_BASE_ADDR + LEV2_INTH_SOURCE_BIN_FIQ_REG_OFFSET)
#define LEV2_INTH_SIR_FIQ_CODE_FIQ_NUM_POS 0
#define LEV2_INTH_SIR_FIQ_CODE_FIQ_NUM_NUMB 5
#define LEV2_INTH_SIR_FIQ_CODE_FIQ_NUM_RES_VAL 0x0
#define LEV2_INTH_SIR_FIQ_CODE_FIQ_NUM_MASK 0x1F
//R
//ARMINTH_CONTROL_REG
//-------------------
#define LEV2_INTH_CONTROL_REG REG32(LEV2_INTH_BASE_ADDR + LEV2_INTH_CTRL_REG_OFFSET)
#define LEV2_INTH_CONTROL_REG_REG (LEV2_INTH_BASE_ADDR + LEV2_INTH_CTRL_REG_OFFSET)
#define LEV2_INTH_CONTROL_REG_NEW_FIQ_AGR_POS 1
#define LEV2_INTH_CONTROL_REG_NEW_FIQ_AGR_NUMB 1
#define LEV2_INTH_CONTROL_REG_NEW_FIQ_AGR_RES_VAL 0x0
//R/W
#define LEV2_INTH_CONTROL_REG_NEW_IRQ_AGR_POS 0
#define LEV2_INTH_CONTROL_REG_NEW_IRQ_AGR_NUMB 1
#define LEV2_INTH_CONTROL_REG_NEW_IRQ_AGR_RES_VAL 0x0
//R/W
//ARMINTH_ILRx
//-------------------
#define LEV2_INTH_ILRx_PRIORITY_POS 2
#define LEV2_INTH_ILRx_PRIORITY_NUMB 5
#define LEV2_INTH_ILRx_PRIORITY_RES_VAL 0x0
//R/W
#define LEV2_INTH_ILRx_SENS_EDGE_POS 1
#define LEV2_INTH_ILRx_SENS_EDGE_NUMB 1
#define LEV2_INTH_ILRx_SENS_EDGE_RES_VAL 0x0
//R/W
#define LEV2_INTH_ILRx_FIQ_POS 0
#define LEV2_INTH_ILRx_FIQ_NUMB 1
#define LEV2_INTH_ILRx_FIQ_RES_VAL 0x0
//R/W
//Macro to access all ILR
#define LEV2_INTH_ILRx(IndexInterrupt) REG32(LEV2_INTH_BASE_ADDR + LEV2_INTH_IT_LEVEL_REG_OFFSET+IndexInterrupt)
#define LEV2_INTH_ILRx_ADD (LEV2_INTH_BASE_ADDR + LEV2_INTH_IT_LEVEL_REG_OFFSET)
//ARMINTH_ISR
//-------------------
#define LEV2_INTH_ISR REG32(LEV2_INTH_BASE_ADDR + LEV2_INTH_SISR_REG_OFFSET)
#define LEV2_INTH_ISR_REG (LEV2_INTH_BASE_ADDR + LEV2_INTH_SISR_REG_OFFSET)
#define LEV2_INTH_ISR_SISR_POS 0
#define LEV2_INTH_ISR_SISR_NUMB 32
#define LEV2_INTH_ISR_SISR_RES_VAL 0x0
//R/W
//##################################################################
// INTERRUPT CONFIGURATION
//##################################################################
#define LEV1_INTH_FIQNIRQ_0 0
#define LEV1_INTH_FIQNIRQ_1 1
#define LEV1_INTH_FIQNIRQ_2 2
#define LEV1_INTH_FIQNIRQ_3 3
#define LEV1_INTH_FIQNIRQ_4 4
#define LEV1_INTH_FIQNIRQ_5 5
#define LEV1_INTH_FIQNIRQ_6 6
#define LEV1_INTH_FIQNIRQ_7 7
#define LEV1_INTH_FIQNIRQ_8 8
#define LEV1_INTH_FIQNIRQ_9 9
#define LEV1_INTH_FIQNIRQ_10 10
#define LEV1_INTH_FIQNIRQ_11 11
#define LEV1_INTH_FIQNIRQ_12 12
#define LEV1_INTH_FIQNIRQ_13 13
#define LEV1_INTH_FIQNIRQ_14 14
#define LEV1_INTH_FIQNIRQ_15 15
#define LEV1_INTH_FIQNIRQ_16 16
#define LEV1_INTH_FIQNIRQ_17 17
#define LEV1_INTH_FIQNIRQ_18 18
#define LEV1_INTH_FIQNIRQ_19 19
#define LEV1_INTH_FIQNIRQ_20 20
#define LEV1_INTH_FIQNIRQ_21 21
#define LEV1_INTH_FIQNIRQ_22 22
#define LEV1_INTH_FIQNIRQ_23 23
#define LEV1_INTH_FIQNIRQ_24 24
#define LEV1_INTH_FIQNIRQ_25 25
#define LEV1_INTH_FIQNIRQ_26 26
#define LEV1_INTH_FIQNIRQ_27 27
#define LEV1_INTH_FIQNIRQ_28 28
#define LEV1_INTH_FIQNIRQ_29 29
#define LEV1_INTH_FIQNIRQ_30 30
#define LEV1_INTH_FIQNIRQ_31 31
#define LEV2_INTH_FIQNIRQ_0 0
#define LEV2_INTH_FIQNIRQ_1 1
#define LEV2_INTH_FIQNIRQ_2 2
#define LEV2_INTH_FIQNIRQ_3 3
#define LEV2_INTH_FIQNIRQ_4 4
#define LEV2_INTH_FIQNIRQ_5 5
#define LEV2_INTH_FIQNIRQ_6 6
#define LEV2_INTH_FIQNIRQ_7 7
#define LEV2_INTH_FIQNIRQ_8 8
#define LEV2_INTH_FIQNIRQ_9 9
#define LEV2_INTH_FIQNIRQ_10 10
#define LEV2_INTH_FIQNIRQ_11 11
#define LEV2_INTH_FIQNIRQ_12 12
#define LEV2_INTH_FIQNIRQ_13 13
#define LEV2_INTH_FIQNIRQ_14 14
#define LEV2_INTH_FIQNIRQ_15 15
#define LEV2_INTH_FIQNIRQ_16 16
#define LEV2_INTH_FIQNIRQ_17 17
#define LEV2_INTH_FIQNIRQ_18 18
#define LEV2_INTH_FIQNIRQ_19 19
#define LEV2_INTH_FIQNIRQ_20 20
#define LEV2_INTH_FIQNIRQ_21 21
#define LEV2_INTH_FIQNIRQ_22 22
#define LEV2_INTH_FIQNIRQ_23 23
#define LEV2_INTH_FIQNIRQ_24 24
#define LEV2_INTH_FIQNIRQ_25 25
#define LEV2_INTH_FIQNIRQ_26 26
#define LEV2_INTH_FIQNIRQ_27 27
#define LEV2_INTH_FIQNIRQ_28 28
#define LEV2_INTH_FIQNIRQ_29 29
#define LEV2_INTH_FIQNIRQ_30 30
#define LEV2_INTH_FIQNIRQ_31 31
//#########################################
// Interrupt Index
//#########################################
#define INTH_INDEX_0 0
#define INTH_INDEX_1 1
#define INTH_INDEX_2 2
#define INTH_INDEX_3 3
#define INTH_INDEX_4 4
#define INTH_INDEX_5 5
#define INTH_INDEX_6 6
#define INTH_INDEX_7 7
#define INTH_INDEX_8 8
#define INTH_INDEX_9 9
#define INTH_INDEX_10 10
#define INTH_INDEX_11 11
#define INTH_INDEX_12 12
#define INTH_INDEX_13 13
#define INTH_INDEX_14 14
#define INTH_INDEX_15 15
#define INTH_INDEX_16 16
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