📄 omap30_arminth.h
字号:
//-------------------------------------------------------------------------------
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reprofuction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work
// Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved
//
//-------------------------------------------------------------------------------
#ifndef _OMAP30_ARMINTH__H_
#define _OMAP30_ARMINTH__H_
//-------------------------------------------------------------------------------
//
// ARM REGISTERS DECLARATION
//
//-------------------------------------------------------------------------------
#define ARMINTH_BASE_ADDR 0xFFFECB00
#define ARMINTH_IT_REG_OFFSET 0x00 /* Interrupt register offset */
#define ARMINTH_MASK_IT_REG_OFFSET 0x04 /* Mask Interrupt register offset */
#define ARMINTH_SOURCE_IRQ_REG_OFFSET 0x08 /* Srce Binary coded IRQ register offset */
#define ARMINTH_SOURCE_FIQ_REG_OFFSET 0x0C /* Srce Binary coded FIQ register offset */
#define ARMINTH_SOURCE_BIN_IRQ_REG_OFFSET 0x10 /* Srce Binary coded IRQ register offset */
#define ARMINTH_SOURCE_BIN_FIQ_REG_OFFSET 0x14 /* Srce Binary coded FIQ register offset */
#define ARMINTH_CTRL_REG_OFFSET 0x18 /* Control register offset */
#define ARMINTH_IT_LEVEL_REG_OFFSET 0x1C /* Interrupt Level registers offset */
#define ARMINTH_SISR_REG_OFFSET 0x9C /* Software Interrupt Set Register offset */
//ARMINTH_ITR
//-------------------
#define ARMINTH_ITR REG32(ARMINTH_BASE_ADDR+ARMINTH_IT_REG_OFFSET)
#define ARMINTH_ITR_REG (ARMINTH_BASE_ADDR+ARMINTH_IT_REG_OFFSET)
#define ARMINTH_ITR_ACT_IRQ_POS 0
#define ARMINTH_ITR_ACT_IRQ_NUMB 32
#define ARMINTH_ITR_ACT_IRQ_RES_VAL 0x0000
//R/W
//ARMINTH_MIR
//-------------------
#define ARMINTH_MIR REG32(ARMINTH_BASE_ADDR+ARMINTH_MASK_IT_REG_OFFSET)
#define ARMINTH_MIR_REG (ARMINTH_BASE_ADDR+ARMINTH_MASK_IT_REG_OFFSET)
#define ARMINTH_MIR_IRQ_MSK_POS 0
#define ARMINTH_MIR_IRQ_MSK_NUMB 32
#define ARMINTH_MIR_IRQ_MSK_RES_VAL 0xFFFF
//R/W
//ARMINTH_SIR_IRQ_CODE
//-------------------
#define ARMINTH_SIR_IRQ_CODE REG32(ARMINTH_BASE_ADDR+ARMINTH_SOURCE_BIN_IRQ_REG_OFFSET)
#define ARMINTH_SIR_IRQ_CODE_REG (ARMINTH_BASE_ADDR+ARMINTH_SOURCE_BIN_IRQ_REG_OFFSET)
#define ARMINTH_SIR_IRQ_CODE_IRQ_NUM_POS 0
#define ARMINTH_SIR_IRQ_CODE_IRQ_NUM_NUMB 5
#define ARMINTH_SIR_IRQ_CODE_IRQ_NUM_RES_VAL 0x0
#define ARMINTH_SIR_IRQ_CODE_IRQ_NUM_MASK 0x001f
//R
//ARMINTH_SIR_FIQ_CODE
//-------------------
#define ARMINTH_SIR_FIQ_CODE REG32(ARMINTH_BASE_ADDR+ARMINTH_SOURCE_BIN_FIQ_REG_OFFSET)
#define ARMINTH_SIR_FIQ_CODE_REG (ARMINTH_BASE_ADDR+ARMINTH_SOURCE_BIN_FIQ_REG_OFFSET)
#define ARMINTH_SIR_FIQ_CODE_FIQ_NUM_POS 0
#define ARMINTH_SIR_FIQ_CODE_FIQ_NUM_NUMB 5
#define ARMINTH_SIR_FIQ_CODE_FIQ_NUM_RES_VAL 0x0
#define ARMINTH_SIR_FIQ_CODE_FIQ_NUM_MASK 0x001f
//R
//ARMINTH_CONTROL_REG
//-------------------
#define ARMINTH_CONTROL_REG REG32(ARMINTH_BASE_ADDR+ARMINTH_CTRL_REG_OFFSET)
#define ARMINTH_CONTROL_REG_REG (ARMINTH_BASE_ADDR+ARMINTH_CTRL_REG_OFFSET)
#define ARMINTH_CONTROL_REG_NEW_FIQ_AGR_POS 1
#define ARMINTH_CONTROL_REG_NEW_FIQ_AGR_NUMB 1
#define ARMINTH_CONTROL_REG_NEW_FIQ_AGR_RES_VAL 0x0
//R/W
#define ARMINTH_CONTROL_REG_NEW_IRQ_AGR_POS 0
#define ARMINTH_CONTROL_REG_NEW_IRQ_AGR_NUMB 1
#define ARMINTH_CONTROL_REG_NEW_IRQ_AGR_RES_VAL 0x0
//R/W
//ARMINTH_ILRx
//-------------------
#define ARMINTH_ILRx_PRIORITY_POS 2
#define ARMINTH_ILRx_PRIORITY_NUMB 5
#define ARMINTH_ILRx_PRIORITY_RES_VAL 0x0
//R/W
#define ARMINTH_ILRx_SENS_EDGE_POS 1
#define ARMINTH_ILRx_SENS_EDGE_NUMB 1
#define ARMINTH_ILRx_SENS_EDGE_RES_VAL 0x0
//R/W
#define ARMINTH_ILRx_FIQ_POS 0
#define ARMINTH_ILRx_FIQ_NUMB 1
#define ARMINTH_ILRx_FIQ_RES_VAL 0x0
//R/W
//Macro to access all ILR
#define ARMINTH_ILRx(IndexInterrupt) REG32(ARMINTH_BASE_ADDR+ARMINTH_IT_LEVEL_REG_OFFSET+IndexInterrupt)
#define ARMINTH_ILRx_ADD (ARMINTH_BASE_ADDR+ARMINTH_IT_LEVEL_REG_OFFSET)
//ARMINTH_ISR
//-------------------
#define ARMINTH_ISR REG32(ARMINTH_BASE_ADDR+ARMINTH_SISR_REG_OFFSET)
#define ARMINTH_ISR_REG (ARMINTH_BASE_ADDR+ARMINTH_SISR_REG_OFFSET)
#define ARMINTH_ISR_SISR_POS 0
#define ARMINTH_ISR_SISR_NUMB 32
#define ARMINTH_ISR_SISR_RES_VAL 0x0
//R/W
//-------------------------------------------------------------------------------
//
// GLOBAL DEFINES
//
//-------------------------------------------------------------------------------
#define INTH_INDEX_0 0
#define INTH_INDEX_1 1
#define INTH_INDEX_2 2
#define INTH_INDEX_3 3
#define INTH_INDEX_4 4
#define INTH_INDEX_5 5
#define INTH_INDEX_6 6
#define INTH_INDEX_7 7
#define INTH_INDEX_8 8
#define INTH_INDEX_9 9
#define INTH_INDEX_10 10
#define INTH_INDEX_11 11
#define INTH_INDEX_12 12
#define INTH_INDEX_13 13
#define INTH_INDEX_14 14
#define INTH_INDEX_15 15
#define INTH_INDEX_16 16
#define INTH_INDEX_17 17
#define INTH_INDEX_18 18
#define INTH_INDEX_19 19
#define INTH_INDEX_20 20
#define INTH_INDEX_21 21
#define INTH_INDEX_22 22
#define INTH_INDEX_23 23
#define INTH_INDEX_24 24
#define INTH_INDEX_25 25
#define INTH_INDEX_26 26
#define INTH_INDEX_27 27
#define INTH_INDEX_28 28
#define INTH_INDEX_29 29
#define INTH_INDEX_30 30
#define INTH_INDEX_31 31
#define FALLING_EDGE_SENSITIVE 0
#define LOW_LEVEL_SENSITIVE 1
#define INTH_FALLING_EDGE_SENSITIVE FALLING_EDGE_SENSITIVE
#define INTH_LOW_LEVEL_SENSITIVE LOW_LEVEL_SENSITIVE
#define INTH_HIGHEST_PRIORITY 0
#define INTH_LOWEST_PRIORITY 31
#define INTH_IRQ 0
#define INTH_FIQ 1
//-------------------------------------------------------------------------------
//
// FUNCTIONS
//
//-------------------------------------------------------------------------------
//-------------------------------------------------------------------------------
// NAME : INTH_InitLevel
// DESCRIPTION : Writes Level Register (Mask or Unmask interrupts)
// PARAMETERS : UWORD8 ItIndex See omap3.h
// BOOL Fiq_or_Irq INTH_FIQ or INTH_IRQ
// UWORD8 Priority from 0 to 31
// BOOL SensitiveEdge FALLING_EDGE_SENSITIVE or LOW_LEVEL_SENSITIVE
// RETURN VALUE: None
// LIMITATIONS : None
//-------------------------------------------------------------------------------
void INTH_InitLevel (UWORD8 ItIndex, BOOL Fiq_or_Irq, UWORD8 Priority, BOOL SensitiveEdge);
//-------------------------------------------------------------------------------
// NAME : INTH_GetCurrentIt
// DESCRIPTION : Get the current It
// PARAMETERS : Fiq_or_Irq: INTH_IRQ or INTH_FIQ
// RETURN VALUE: Number of the active and acknowledged Interrupt
// LIMITATIONS : Must be called on Incoming IT
//-------------------------------------------------------------------------------
UWORD8 INTH_GetCurrentIt (BOOL Fiq_or_Irq);
//-------------------------------------------------------------------------------
// NAME : INTH_ValidNextInterrupt
// DESCRIPTION : Valid the next IT depending on the current one
// PARAMETERS : Fiq_or_Irq: INTH_IRQ or INTH_FIQ
// RETURN VALUE: None
// LIMITATIONS : Must be called on Incoming IT
//-------------------------------------------------------------------------------
void INTH_ValidNextInterrupt (BOOL Fiq_or_Irq);
//-------------------------------------------------------------------------------
// NAME : INTH_ClearInt
// DESCRIPTION : Clear the an IT when IT is not enabled (outside of a routine)
// Prefer use ValidNext in a routine
// PARAMETERS : ItNumber
// RETURN VALUE: None
// LIMITATIONS : None
//-------------------------------------------------------------------------------
void INTH_ClearInt(UWORD8 ItIndex);
//-------------------------------------------------------------------------------
// NAME : INTH_EnableOneIT
// DESCRIPTION : Enable one interrupt
// PARAMETERS : UWORD8 ItIndex See omap3.h
// RETURN VALUE: None
// LIMITATIONS : None
//-------------------------------------------------------------------------------
void INTH_EnableOneIT(UWORD8 ItIndex);
//-------------------------------------------------------------------------------
// NAME : INTH_DisableOneIT
// DESCRIPTION : Disable one interrupt
// PARAMETERS : UWORD8 ItIndex
// RETURN VALUE: None
// LIMITATIONS : None
//-------------------------------------------------------------------------------
void INTH_DisableOneIT(UWORD32 ItIndex);
#endif /* _OMAP30_ARMINTH__H_ */
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -