omap30_clkrst.h

有关于USB的一些主机端驱动

//R/W

#define            DPLL_DPLL3_CTL_REG_PLL_MULT_POS                             7
#define            DPLL_DPLL3_CTL_REG_PLL_MULT_NUMB                            5
#define            DPLL_DPLL3_CTL_REG_PLL_MULT_RES_VAL                         0x0
//R/W

#define            DPLL_DPLL3_CTL_REG_PLL_DIV_POS                              5
#define            DPLL_DPLL3_CTL_REG_PLL_DIV_NUMB                             2
#define            DPLL_DPLL3_CTL_REG_PLL_DIV_RES_VAL                          0x0
//R/W

#define            DPLL_DPLL3_CTL_REG_PLL_ENABLE_POS                           4
#define            DPLL_DPLL3_CTL_REG_PLL_ENABLE_NUMB                          1
#define            DPLL_DPLL3_CTL_REG_PLL_ENABLE_RES_VAL                       0x0
//R/W

#define            DPLL_DPLL3_CTL_REG_BYPASS_DIV_POS                           2
#define            DPLL_DPLL3_CTL_REG_BYPASS_DIV_NUMB                          2
#define            DPLL_DPLL3_CTL_REG_BYPASS_DIV_RES_VAL                       0x0
//R/W

#define            DPLL_DPLL3_CTL_REG_BREAKLN_POS                              1
#define            DPLL_DPLL3_CTL_REG_BREAKLN_NUMB                             1
#define            DPLL_DPLL3_CTL_REG_BREAKLN_RES_VAL                          0x0
//R

#define            DPLL_DPLL3_CTL_REG_LOCK_POS                                 0
#define            DPLL_DPLL3_CTL_REG_LOCK_NUMB                                1
#define            DPLL_DPLL3_CTL_REG_LOCK_RES_VAL                             0x0
//R

//-------------------------------------------------------------------------------
//
//   GLOBAL TYPES DEFINITION
//
//-------------------------------------------------------------------------------

// name of periph (enable clocks)
typedef enum {

  WDGTIM_CK,
  XORPC_CK,
  PER_CK,
  LCD_CK,
  LB_CK,
  HSAB_CK,
  API_CK,
  TIM_CK,
  DMA_REQ_CK,
  GPIO_CK,
  LBFREE_CK,
  ALL_CK       
      
} CLOCK_SWITCH_t;

typedef enum {

  DSP_WDGTIM_CK,
  DSP_XORPC_CK,
  DSP_PER_CK,
  DSP_UART_CK,
  DSP_GPIO_CK,
  DSP_TIM_CK,
  DSP_ALL_CK       
      
} DSP_CLOCK_SWITCH_t;

 typedef enum { DPLL1, DPLL2, DPLL3 } DPLLTYPE_t;


#define SET_IN_IDLE                       TRUE
#define SET_NOT_IDLE                      FALSE

#define IDLE_PIN_WKUP                     FALSE
#define IDLE_INT_WKUP                     TRUE

// define to treat DMA flag
#define STOP_BY_DEFAULT                   TRUE
#define ONLY_WHEN_IDLE                    FALSE

typedef enum {

  DSPMMU_DIV,
  TC_DIV,
  DSP_DIV,
  ARM_DIV,
  LCD_DIV,
  PER_DIV           

} DIV_NAME_t;

typedef enum {

  CLK_DIV_BY_1=0,
  CLK_DIV_BY_2=1,
  CLK_DIV_BY_4=2,
  CLK_DIV_BY_8=3

} CKCTL_DIV_t;

typedef enum {

  TIMARM_MODULE_IDLE,
  APIARM_MODULE_IDLE,
  DPLLARM_MODULE_IDLE,
  LIFARM_MODULE_IDLE,
  HSABARM_MODULE_IDLE,
  LBARM_MODULE_IDLE,
  LCDARM_MODULE_IDLE,
  PERARM_MODULE_IDLE,
  XORPARM_MODULE_IDLE,
  WDTARM_MODULE_IDLE,
  ALL_IDLE

} MODULE_IDLE_NAME_t;

typedef enum {
  SYNC_MODE_CK = 0,
  ASYNC_MODE_CK = 1,
  SCAL_MODE_CK = 2,
  ARM_TOTC_MODE_CK = 3,
  MGS3_TOTC_MODE_CK = 4,
  BYPASS_MODE_CK = 5,
  TEST_MODE_CK = 6
} CLOCK_MODE_t;


typedef enum
{
  GLOBAL_RESET = 0,
  MCU_RESET = 1
} Reset_t;


typedef enum
{
  NONE        = 0,
  DSP_WDG_RST = 1,
  GLB_SW_RST  = 2,
  ARM_WDG_RST = 4,
  ARM_MCU_RST = 8,
  EXT_RST     = 16,
  POWER_ON_RST = 32
} SourceReset_t;


//-------------------------------------------------------------------------------
//
//  FUNCTIONS
//
//-------------------------------------------------------------------------------

//-------------------------------------------------------------------------------
// NAME        : DpllSetClockandLock
// DESCRIPTION : Modify the value output from dpll
// PARAMETERS  : multiplier       a value which belong  : 1-31
//               divider          a value which belong  : 1-4
// RETURN VALUE: IS_OK if correct NOT_OK if not
// LIMITATIONS : None
//-------------------------------------------------------------------------------
BOOL CLKRST_DpllSetClockandLock( UWORD8 multiplier , UWORD8 divider, DPLLTYPE_t  dpllreglabel);

//-------------------------------------------------------------------------------
// NAME        : CLKRST_SetPeripheralClockEnable 
// DESCRIPTION : Enable/Disable the selected peripheral clock
// PARAMETERS  : PerifName
//                         WDGTIM_CK,   
//                         XORPC_CK,    
//                         PER_CK,      
//                         LCD_CK,      
//                         LB_CK,       
//                         HSAB_CK,     
//                         API_CK,      
//                         TIM_CK,      
//                         DMA_REQ_CK,  
//                         GPIO_CK,     
//                         LBFREE_CK,   
//                         ALL_CK        
//                and State=ENABLE or DISABLE
// RETURN VALUE: IS_OK if the operation succeed
//               NOT_OK if not     
//  LIMITATIONS : None                                     
//-------------------------------------------------------------------------------
BOOL CLKRST_SetPeripheralClockEnable(CLOCK_SWITCH_t PerifName, BOOL State);

//-------------------------------------------------------------------------------
// NAME         : CLKRST_DriveDspReset                                              
// DESCRIPTION  : drive the reset line of the dsp
// PARAMETERS   : level HIGH_LEVEL or LOW_LEVEL
// RETURN VALUE : None 
// LIMITATIONS  : None                              
//-------------------------------------------------------------------------------
void CLKRST_DriveDspReset(BOOL level);

//-------------------------------------------------------------------------------
// NAME         : CLKRST_GenerateReset                                              
// DESCRIPTION  : Reset OMAP3
// PARAMETERS   : GLOBAL_RESET or MCU_RESET
// RETURN VALUE : None 
// LIMITATIONS  : None                                  
//-------------------------------------------------------------------------------
void CLKRST_GenerateReset(Reset_t Domain);

//-------------------------------------------------------------------------------
// NAME         : CLKRST_GetResetOrigin                                              
// DESCRIPTION  : Reset OMAP3
// PARAMETERS   : None
// RETURN VALUE : 	NONE
//			DSP_WDG_RST
//			GLB_SW_RST
//			ARM_WDG_RST
//			ARM_MCU_RS
//			EXT_RST
//			POWER_ON_RST  
// LIMITATIONS  : None                                  
//-------------------------------------------------------------------------------
SourceReset_t CLKRST_GetResetOrigin(void);

//-------------------------------------------------------------------------------
// NAME         : CLKRST_EnableDisableDsp                                             
// DESCRIPTION  : Reset the priority registers, Emifs confs and API control
// PARAMETERS   : level HIGH_LEVEL or LOW_LEVEL
// RETURN VALUE : None 
// LIMITATIONS  : None                              
//-------------------------------------------------------------------------------
void CLKRST_DriveInterfaceDspReset(BOOL level);

//-------------------------------------------------------------------------------
// NAME         : CLKRST_EnableDisableDspClock
// DESCRIPTION  : Enable or disable the dsp clock to turned on during the reset state
// PARAMETERS   : Action ENABLE or DISABLE
// RETURN VALUE : None 
// LIMITATIONS  : None                              
//-------------------------------------------------------------------------------
void CLKRST_EnableDisableDspClock(BOOL Action);

//-------------------------------------------------------------------------------
// NAME         : CLKRST_SetIdle               
// DESCRIPTION  : Launch the idle mode                  
// PARAMETERS   : IdleMode         IDLE_PIN_WKUP or IDLE_INT_WKUP 
// RETURN VALUE : None.                                                     
// LIMITATIONS  : None                                                      
//-------------------------------------------------------------------------------
void CLKRST_SetIdle(BOOL IdleMode);

//-------------------------------------------------------------------------------
// NAME         : CLKRST_TogglePeripheralResetPin       
// DESCRIPTION  : Toggle the pin which manage the peripheral reset :MCUPER_nRST
// PARAMETERS   : LOW_LEVEL or HIGH_LEVEL
// RETURN VALUE : None 
// LIMITATIONS  : None                                   
//-------------------------------------------------------------------------------
void CLKRST_TogglePeripheralResetPin(BOOL State);

//-------------------------------------------------------------------------------
// NAME         : SetClockDivider                     
// DESCRIPTION  : defines the frequency for sub domain
// PARAMETERS   : CLOCK_DIV values of peripherals     
//                   DSPMMU_DIV                   
//                   TC_DIV                       
//                   DSP_DIV                      
//                   ARM_DIV                      
//                   LCD_DIV                      
//                   PER_DIV                      
//                    CLK_DIV_BY_1                     
//                    CLK_DIV_BY_2                     
//                    CLK_DIV_BY_4                     
//                    CLK_DIV_BY_8                     
// RETURN VALUE : None.                               
// LIMITATIONS  : None                                
//-------------------------------------------------------------------------------
void CLKRST_SetClockDivider(DIV_NAME_t DivName,  CKCTL_DIV_t divval);

//-------------------------------------------------------------------------------
// NAME         : CLKRST_ConfigIdleModule                                          
// DESCRIPTION  : put or remove a module from idle mode                 
// PARAMETERS   : Module2set	TIMARM_MODULE_IDLE
//				APIARM_MODULE_IDLE
//				DPLLARM_MODULE_IDLE
//				LIFARM_MODULE_IDLE
//				HSABARM_MODULE_IDLE
//				LBARM_MODULE_IDLE
//				LCDARM_MODULE_IDLE
//				PERARM_MODULE_IDLE:
//				XORPARM_MODULE_IDLE
//				WDTARM_MODULE_IDLE
//				ALL_IDLE
//               State          SET_IN_IDLE or SET_NOT_IDLE
// RETURN VALUE : None.                                                    
// LIMITATIONS  : None                                                    
//-------------------------------------------------------------------------------
void CLKRST_ConfigIdleModule(MODULE_IDLE_NAME_t Module2Set, BOOL State  );

//-------------------------------------------------------------------------------
// NAME        : CLKRST_SetDspPeripheralClockEnable 
// DESCRIPTION : Enable/Disable the selected peripheral clock
// PARAMETERS  : PerifName
//                        DSP_WDGTIM_CK   
//                        DSP_XORPC_CK    
//                        DSP_PER_CK      
//                        DSP_UART_CK     
//                        DSP_GPIO_CK     
//                        DSP_TIM_CK      
//                        DSP_ALL_CK       
//                                   
//                and State=ENABLE or DISABLE
// RETURN VALUE: IS_OK if the operation succeed
//               NOT_OK if not    
//  LIMITATIONS : None                                    
//-------------------------------------------------------------------------------
BOOL CLKRST_SetDspPeripheralClockEnable(DSP_CLOCK_SWITCH_t PerifName, BOOL State);

//-------------------------------------------------------------------------------
// NAME         : CLKRST_SetClockMode
// DESCRIPTION  : Set the clock mode
// PARAMETERS   :   - SYNC_MODE_CK 
//                  - ASYNC_MODE_CK
//                  - SCAL_MODE_CK
//                  - ARM_TO_TC_MODE_CK
//                  - DSP_TO_TC_MODE_CK
//                  - BYPASS_MODE_CK
//                  - TEST_MODE_CK
// RETURN VALUE : None                                                      
// LIMITATIONS  : None
//-------------------------------------------------------------------------------
void CLKRST_SetClockMode(CLOCK_MODE_t ClockMode);

#endif   /* _OMAP30_CLKRST__H_ */