📄 omap30_clkrst.h
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//DSPCLKM_DSP_CKTL
//-------------------
#define DSPCLKM_DSP_CKTL REG16(DSPCLKM_BASE_ADDR+0x00)
#define DSPCLKM_DSP_CKTL_TIMXO_POS 8
#define DSPCLKM_DSP_CKTL_TIMXO_NUMB 1
#define DSPCLKM_DSP_CKTL_TIMXO_RES_VAL 0x1
//R/W
#define DSPCLKM_DSP_CKTL_GPIOX0_POS 7
#define DSPCLKM_DSP_CKTL_GPIOX0_NUMB 1
#define DSPCLKM_DSP_CKTL_GPIOX0_RES_VAL 0x1
//R/W
#define DSPCLKM_DSP_CKTL_GPIODIV_POS 5
#define DSPCLKM_DSP_CKTL_GPIODIV_NUMB 2
#define DSPCLKM_DSP_CKTL_GPIODIV_RES_VAL 0x0
//R/W
#define DSPCLKM_DSP_CKTL_UARTX0_POS 4
#define DSPCLKM_DSP_CKTL_UARTX0_NUMB 1
#define DSPCLKM_DSP_CKTL_UARTX0_RES_VAL 0x1
//R/W
#define DSPCLKM_DSP_CKTL_UARTDIV_POS 2
#define DSPCLKM_DSP_CKTL_UARTDIV_NUMB 2
#define DSPCLKM_DSP_CKTL_UARTDIV_RES_VAL 0x0
//R/W
#define DSPCLKM_DSP_CKTL_PERDIV_POS 0
#define DSPCLKM_DSP_CKTL_PERDIV_NUMB 2
#define DSPCLKM_DSP_CKTL_PERDIV_RES_VAL 0X0
//R/W
//DSPCLKM_DSP_IDLECT1
//-------------------
#define DSPCLKM_DSP_IDLECT1 REG16(DSPCLKM_BASE_ADDR+0x04)
#define DSPCLKM_DSP_IDLECT1_IDLTIM_DSP_POS 8
#define DSPCLKM_DSP_IDLECT1_IDLTIM_DSP_NUMB 1
#define DSPCLKM_DSP_IDLECT1_IDLTIM_DSP_RES_VAL 0x0
//R/W
#define DSPCLKM_DSP_IDLECT1_IDLGPIO_DSP_POS 7
#define DSPCLKM_DSP_IDLECT1_IDLGPIO_DSP_NUMB 1
#define DSPCLKM_DSP_IDLECT1_IDLGPIO_DSP_RES_VAL 0x0
//R/W
#define DSPCLKM_DSP_IDLECT1_WKUP_MODE_POS 6
#define DSPCLKM_DSP_IDLECT1_WKUP_MODE_NUMB 1
#define DSPCLKM_DSP_IDLECT1_WKUP_MODE_RES_VAL 0x1
//R/W
#define DSPCLKM_DSP_IDLECT1_IDLDPLL_DSP_POS 5
#define DSPCLKM_DSP_IDLECT1_IDLDPLL_DSP_NUMB 1
#define DSPCLKM_DSP_IDLECT1_IDLDPLL_DSP_RES_VAL 0x0
//R/W
#define DSPCLKM_DSP_IDLECT1_IDLIF_DSP_POS 4
#define DSPCLKM_DSP_IDLECT1_IDLIF_DSP_NUMB 1
#define DSPCLKM_DSP_IDLECT1_IDLIF_DSP_RES_VAL 0x0
//R/W
#define DSPCLKM_DSP_IDLECT1_IDLUART_DSP_POS 3
#define DSPCLKM_DSP_IDLECT1_IDLUART_DSP_NUMB 1
#define DSPCLKM_DSP_IDLECT1_IDLUART_DSP_RES_VAL 0x0
//R/W
#define DSPCLKM_DSP_IDLECT1_IDLPER_DSP_POS 2
#define DSPCLKM_DSP_IDLECT1_IDLPER_DSP_NUMB 1
#define DSPCLKM_DSP_IDLECT1_IDLPER_DSP_RES_VAL 0x0
//R/W
#define DSPCLKM_DSP_IDLECT1_IDLXORP_DSP_POS 1
#define DSPCLKM_DSP_IDLECT1_IDLXORP_DSP_NUMB 1
#define DSPCLKM_DSP_IDLECT1_IDLXORP_DSP_RES_VAL 0x0
//R/W
#define DSPCLKM_DSP_IDLECT1_IDLWDT_DSP_POS 0
#define DSPCLKM_DSP_IDLECT1_IDLWDT_DSP_NUMB 1
#define DSPCLKM_DSP_IDLECT1_IDLWDT_DSP_RES_VAL 0x0
//R/W
//DSPCLKM_DSP_IDLECT2
//-------------------
#define DSPCLKM_DSP_IDLECT2 REG16(DSPCLKM_BASE_ADDR+0x08)
#define DSPCLKM_DSP_IDLECT2_EN_TIMCK_POS 5
#define DSPCLKM_DSP_IDLECT2_EN_TIMCK_NUMB 1
#define DSPCLKM_DSP_IDLECT2_EN_TIMCK_RES_VAL 0x0
//R/W
#define DSPCLKM_DSP_IDLECT2_EN_GPIOCK_POS 4
#define DSPCLKM_DSP_IDLECT2_EN_GPIOCK_NUMB 1
#define DSPCLKM_DSP_IDLECT2_EN_GPIOCK_RES_VAL 0x0
//R/W
#define DSPCLKM_DSP_IDLECT2_EN_UARTCK_POS 3
#define DSPCLKM_DSP_IDLECT2_EN_UARTCK_NUMB 1
#define DSPCLKM_DSP_IDLECT2_EN_UARTCK_RES_VAL 0x0
//R/W
#define DSPCLKM_DSP_IDLECT2_EN_PERCK_POS 2
#define DSPCLKM_DSP_IDLECT2_EN_PERCK_NUMB 1
#define DSPCLKM_DSP_IDLECT2_EN_PERCK_RES_VAL 0x0
//R/W
#define DSPCLKM_DSP_IDLECT2_EN_XORPCK_POS 1
#define DSPCLKM_DSP_IDLECT2_EN_XORPCK_NUMB 1
#define DSPCLKM_DSP_IDLECT2_EN_XORPCK_RES_VAL 0x0
//R/W
#define DSPCLKM_DSP_IDLECT2_EN_WDTCK_POS 0
#define DSPCLKM_DSP_IDLECT2_EN_WDTCK_NUMB 1
#define DSPCLKM_DSP_IDLECT2_EN_WDTCK_RES_VAL 0x0
//R/W
//DSPCLKM_DSP_EWUPCT
//-------------------
#define DSPCLKM_DSP_EWUPCT REG16(DSPCLKM_BASE_ADDR+0x0C)
//DSPCLKM_DSP_RSTCT1
//-------------------
#define DSPCLKM_DSP_RSTCT1 REG16(DSPCLKM_BASE_ADDR+0x10)
//DSPCLKM_DSP_RSTCT2
//-------------------
#define DSPCLKM_DSP_RSTCT2 REG16(DSPCLKM_BASE_ADDR+0x14)
#define DSPCLKM_DSP_RSTCT2_PER_EN_POS 0
#define DSPCLKM_DSP_RSTCT2_PER_EN_NUMB 1
#define DSPCLKM_DSP_RSTCT2_PER_EN_RES_VAL 0x0
//R/W
//DSPCLKM_DSP_SYSST
//-------------------
#define DSPCLKM_DSP_SYSST REG16(DSPCLKM_BASE_ADDR+0x18)
#define DSPCLKM_DSP_SYSST_CLOCK_SELECT_POS 11
#define DSPCLKM_DSP_SYSST_CLOCK_SELECT_NUMB 3
#define DSPCLKM_DSP_SYSST_CLOCK_SELECT_RES_VAL 0x0
//R
#define DSPCLKM_DSP_SYSST_IDLE_ARM_POS 6
#define DSPCLKM_DSP_SYSST_IDLE_ARM_NUMB 1
#define DSPCLKM_DSP_SYSST_IDLE_ARM_RES_VAL 0x0
//R
#define DSPCLKM_DSP_SYSST_POR_POS 5
#define DSPCLKM_DSP_SYSST_POR_NUMB 1
#define DSPCLKM_DSP_SYSST_POR_RES_VAL 0x0
//R/C
#define DSPCLKM_DSP_SYSST_EXT_RST_POS 4
#define DSPCLKM_DSP_SYSST_EXT_RST_NUMB 1
#define DSPCLKM_DSP_SYSST_EXT_RST_RES_VAL 0x0
//R/C
#define DSPCLKM_DSP_SYSST_DSP_ARM_RST_POS 3
#define DSPCLKM_DSP_SYSST_DSP_ARM_RST_NUMB 1
#define DSPCLKM_DSP_SYSST_DSP_ARM_RST_RES_VAL 0x0
//R/W
#define DSPCLKM_DSP_SYSST_ARM_WDRST_POS 2
#define DSPCLKM_DSP_SYSST_ARM_WDRST_NUMB 1
#define DSPCLKM_DSP_SYSST_ARM_WDRST_RES_VAL 0x0
//R/C
#define DSPCLKM_DSP_SYSST_GLOB_SWRST_POS 1
#define DSPCLKM_DSP_SYSST_GLOB_SWRST_NUMB 1
#define DSPCLKM_DSP_SYSST_GLOB_SWRST_RES_VAL 0x0
//R/C
#define DSPCLKM_DSP_SYSST_DSP_WDRST_POS 0
#define DSPCLKM_DSP_SYSST_DSP_WDRST_NUMB 1
#define DSPCLKM_DSP_SYSST_DSP_WDRST_RES_VAL 0x0
//R/C
//DSPCLKM_DSP_CKOUT1
//-------------------
#define DSPCLKM_DSP_CKOUT1 REG16(DSPCLKM_BASE_ADDR+0x1C)
//DSPCLKM_DSP_CKOUT2
//-------------------
#define DSPCLKM_DSP_CKOUT2 REG16(DSPCLKM_BASE_ADDR+0x20)
//-------------------------------------------------------------------------------
//
// DPLL REGISTERS DECLARATION
//
//-------------------------------------------------------------------------------
#define DPLL_BASE_ADDR MEM_ARM_DPLL1_ADDR
//DPLL_DPLL1_CTL_REG
//-------------------
#define DPLL_DPLL1_CTL_REG REG16(DPLL_BASE_ADDR+0x00)
#define DPLL_DPLL1_CTL_REG_IAI_POS 14
#define DPLL_DPLL1_CTL_REG_IAI_NUMB 1
#define DPLL_DPLL1_CTL_REG_IAI_RES_VAL 0x0
//R/W
#define DPLL_DPLL1_CTL_REG_IOB_POS 13
#define DPLL_DPLL1_CTL_REG_IOB_NUMB 1
#define DPLL_DPLL1_CTL_REG_IOB_RES_VAL 0x1
//R/W
#define DPLL_DPLL1_CTL_REG_TEST_POS 12
#define DPLL_DPLL1_CTL_REG_TEST_NUMB 1
#define DPLL_DPLL1_CTL_REG_TEST_RES_VAL 0x0
//R/W
#define DPLL_DPLL1_CTL_REG_PLL_MULT_POS 7
#define DPLL_DPLL1_CTL_REG_PLL_MULT_NUMB 5
#define DPLL_DPLL1_CTL_REG_PLL_MULT_RES_VAL 0x0
//R/W
#define DPLL_DPLL1_CTL_REG_PLL_DIV_POS 5
#define DPLL_DPLL1_CTL_REG_PLL_DIV_NUMB 2
#define DPLL_DPLL1_CTL_REG_PLL_DIV_RES_VAL 0x0
//R/W
#define DPLL_DPLL1_CTL_REG_PLL_ENABLE_POS 4
#define DPLL_DPLL1_CTL_REG_PLL_ENABLE_NUMB 1
#define DPLL_DPLL1_CTL_REG_PLL_ENABLE_RES_VAL 0x0
//R/W
#define DPLL_DPLL1_CTL_REG_BYPASS_DIV_POS 2
#define DPLL_DPLL1_CTL_REG_BYPASS_DIV_NUMB 2
#define DPLL_DPLL1_CTL_REG_BYPASS_DIV_RES_VAL 0x0
//R/W
#define DPLL_DPLL1_CTL_REG_BREAKLN_POS 1
#define DPLL_DPLL1_CTL_REG_BREAKLN_NUMB 1
#define DPLL_DPLL1_CTL_REG_BREAKLN_RES_VAL 0x0
//R
#define DPLL_DPLL1_CTL_REG_LOCK_POS 0
#define DPLL_DPLL1_CTL_REG_LOCK_NUMB 1
#define DPLL_DPLL1_CTL_REG_LOCK_RES_VAL 0x0
//R
//DPLL_DPLL2_CTL_REG
//-------------------
#define DPLL_DPLL2_CTL_REG REG16(DPLL_BASE_ADDR+0x100)
#define DPLL_DPLL2_CTL_REG_IAI_POS 14
#define DPLL_DPLL2_CTL_REG_IAI_NUMB 1
#define DPLL_DPLL2_CTL_REG_IAI_RES_VAL 0x0
//R/W
#define DPLL_DPLL2_CTL_REG_IOB_POS 13
#define DPLL_DPLL2_CTL_REG_IOB_NUMB 1
#define DPLL_DPLL2_CTL_REG_IOB_RES_VAL 0x1
//R/W
#define DPLL_DPLL2_CTL_REG_TEST_POS 12
#define DPLL_DPLL2_CTL_REG_TEST_NUMB 1
#define DPLL_DPLL2_CTL_REG_TEST_RES_VAL 0x0
//R/W
#define DPLL_DPLL2_CTL_REG_PLL_MULT_POS 7
#define DPLL_DPLL2_CTL_REG_PLL_MULT_NUMB 5
#define DPLL_DPLL2_CTL_REG_PLL_MULT_RES_VAL 0x0
//R/W
#define DPLL_DPLL2_CTL_REG_PLL_DIV_POS 5
#define DPLL_DPLL2_CTL_REG_PLL_DIV_NUMB 2
#define DPLL_DPLL2_CTL_REG_PLL_DIV_RES_VAL 0x0
//R/W
#define DPLL_DPLL2_CTL_REG_PLL_ENABLE_POS 4
#define DPLL_DPLL2_CTL_REG_PLL_ENABLE_NUMB 1
#define DPLL_DPLL2_CTL_REG_PLL_ENABLE_RES_VAL 0x0
//R/W
#define DPLL_DPLL2_CTL_REG_BYPASS_DIV_POS 2
#define DPLL_DPLL2_CTL_REG_BYPASS_DIV_NUMB 2
#define DPLL_DPLL2_CTL_REG_BYPASS_DIV_RES_VAL 0x0
//R/W
#define DPLL_DPLL2_CTL_REG_BREAKLN_POS 1
#define DPLL_DPLL2_CTL_REG_BREAKLN_NUMB 1
#define DPLL_DPLL2_CTL_REG_BREAKLN_RES_VAL 0x0
//R
#define DPLL_DPLL2_CTL_REG_LOCK_POS 0
#define DPLL_DPLL2_CTL_REG_LOCK_NUMB 1
#define DPLL_DPLL2_CTL_REG_LOCK_RES_VAL 0x0
//R
//DPLL_DPLL3_CTL_REG
//-------------------
#define DPLL_DPLL3_CTL_REG REG16(DPLL_BASE_ADDR+0x200)
#define DPLL_DPLL3_CTL_REG_IAI_POS 14
#define DPLL_DPLL3_CTL_REG_IAI_NUMB 1
#define DPLL_DPLL3_CTL_REG_IAI_RES_VAL 0x0
//R/W
#define DPLL_DPLL3_CTL_REG_IOB_POS 13
#define DPLL_DPLL3_CTL_REG_IOB_NUMB 1
#define DPLL_DPLL3_CTL_REG_IOB_RES_VAL 0x1
//R/W
#define DPLL_DPLL3_CTL_REG_TEST_POS 12
#define DPLL_DPLL3_CTL_REG_TEST_NUMB 1
#define DPLL_DPLL3_CTL_REG_TEST_RES_VAL 0x0
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