📄 omap30_clkrst.h
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//-------------------------------------------------------------------------------
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reprofuction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work
// Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved
//
//-------------------------------------------------------------------------------
#ifndef _OMAP30_CLKRST__H_
#define _OMAP30_CLKRST__H_
//-------------------------------------------------------------------------------
//
// ARM REGISTERS DECLARATION
//
//-------------------------------------------------------------------------------
#define CLKRST_BASE_ADDR MEM_ARM_CLKM_ADDR
//CLKRST_ARM_CKCTL
//-------------------
#define CLKRST_ARM_CKCTL REG16(CLKRST_BASE_ADDR+0x00)
#define CLKRST_ARM_CKCTL_ARM_INTHCK_POS 14
#define CLKRST_ARM_CKCTL_ARM_INTHCK_NUMB 1
#define CLKRST_ARM_CKCTL_ARM_INTHCK_RES_VAL 0x0
//R/W
#define CLKRST_ARM_CKCTL_EN_DSPCK_POS 13
#define CLKRST_ARM_CKCTL_EN_DSPCK_NUMB 1
#define CLKRST_ARM_CKCTL_EN_DSPCK_RES_VAL 0x1
//R/W
#define CLKRST_ARM_CKCTL_ARM_TIMXO_POS 12
#define CLKRST_ARM_CKCTL_ARM_TIMXO_NUMB 1
#define CLKRST_ARM_CKCTL_ARM_TIMXO_RES_VAL 0x1
//R/W
#define CLKRST_ARM_CKCTL_DSPMMUDIV_POS 10
#define CLKRST_ARM_CKCTL_DSPMMUDIV_NUMB 2
#define CLKRST_ARM_CKCTL_DSPMMUDIV_RES_VAL 0x0
//R/W
#define CLKRST_ARM_CKCTL_TCDIV_POS 8
#define CLKRST_ARM_CKCTL_TCDIV_NUMB 2
#define CLKRST_ARM_CKCTL_TCDIV_RES_VAL 0x0
//R/W
#define CLKRST_ARM_CKCTL_DSPDIV_POS 6
#define CLKRST_ARM_CKCTL_DSPDIV_NUMB 2
#define CLKRST_ARM_CKCTL_DSPDIV_RES_VAL 0x0
//R/W
#define CLKRST_ARM_CKCTL_ARMDIV_POS 4
#define CLKRST_ARM_CKCTL_ARMDIV_NUMB 2
#define CLKRST_ARM_CKCTL_ARMDIV_RES_VAL 0x0
//R/W
#define CLKRST_ARM_CKCTL_LCDDIV_POS 2
#define CLKRST_ARM_CKCTL_LCDDIV_NUMB 2
#define CLKRST_ARM_CKCTL_LCDDIV_RES_VAL 0x0
//RW
#define CLKRST_ARM_CKCTL_PERDIV_POS 0
#define CLKRST_ARM_CKCTL_PERDIV_NUMB 2
#define CLKRST_ARM_CKCTL_PERDIV_RES_VAL 0x0
//RW
//CLKRST_ARM_IDLECT1
//-------------------
#define CLKRST_ARM_IDLECT1 REG16(CLKRST_BASE_ADDR+0x04)
#define CLKRST_ARM_IDLECT1_SETARM_IDLE_POS 11
#define CLKRST_ARM_IDLECT1_SETARM_IDLE_NUMB 1
#define CLKRST_ARM_IDLECT1_SETARM_IDLE_RES_VAL 0x0
//R/W
#define CLKRST_ARM_IDLECT1_WKUP_MODE_POS 10
#define CLKRST_ARM_IDLECT1_WKUP_MODE_NUMB 1
#define CLKRST_ARM_IDLECT1_WKUP_MODE_RES_VAL 0x1
//R/W
#define CLKRST_ARM_IDLECT1_IDLTIM_ARM_POS 9
#define CLKRST_ARM_IDLECT1_IDLTIM_ARM_NUMB 1
#define CLKRST_ARM_IDLECT1_IDLTIM_ARM_RES_VAL 0x0
//R/W
#define CLKRST_ARM_IDLECT1_IDLAPI_ARM_POS 8
#define CLKRST_ARM_IDLECT1_IDLAPI_ARM_NUMB 1
#define CLKRST_ARM_IDLECT1_IDLAPI_ARM_RES_VAL 0X0
//R/W
#define CLKRST_ARM_IDLECT1_IDLDPLL_ARM_POS 7
#define CLKRST_ARM_IDLECT1_IDLDPLL_ARM_NUMB 1
#define CLKRST_ARM_IDLECT1_IDLDPLL_ARM_RES_VAL 0x0
//R/W
#define CLKRST_ARM_IDLECT1_IDLIF_ARM_POS 6
#define CLKRST_ARM_IDLECT1_IDLIF_ARM_NUMB 1
#define CLKRST_ARM_IDLECT1_IDLIF_ARM_RES_VAL 0x0
//R/W
#define CLKRST_ARM_IDLECT1_IDLHSAB_ARM_POS 5
#define CLKRST_ARM_IDLECT1_IDLHSAB_ARM_NUMB 1
#define CLKRST_ARM_IDLECT1_IDLHSAB_ARM_RES_VAL 0x0
//R/W
#define CLKRST_ARM_IDLECT1_IDLLB_ARM_POS 4
#define CLKRST_ARM_IDLECT1_IDLLB_ARM_NUMB 1
#define CLKRST_ARM_IDLECT1_IDLLB_ARM_RES_VAL 0x0
//R/W
#define CLKRST_ARM_IDLECT1_IDLLCD_ARM_POS 3
#define CLKRST_ARM_IDLECT1_IDLLCD_ARM_NUMB 1
#define CLKRST_ARM_IDLECT1_IDLLCD_ARM_RES_VAL 0x0
//R/W
#define CLKRST_ARM_IDLECT1_IDLPER_ARM_POS 2
#define CLKRST_ARM_IDLECT1_IDLPER_ARM_NUMB 1
#define CLKRST_ARM_IDLECT1_IDLPER_ARM_RES_VAL 0x0
//R/W
#define CLKRST_ARM_IDLECT1_IDLXORP_ARM_POS 1
#define CLKRST_ARM_IDLECT1_IDLXORP_ARM_NUMB 1
#define CLKRST_ARM_IDLECT1_IDLXORP_ARM_RES_VAL 0x0
//R/W
#define CLKRST_ARM_IDLECT1_IDLWDT_ARM_POS 0
#define CLKRST_ARM_IDLECT1_IDLWDT_ARM_NUMB 1
#define CLKRST_ARM_IDLECT1_IDLWDT_ARM_RES_VAL 0x0
//R/W
//CLKRST_ARM_IDLECT2
//-------------------
#define CLKRST_ARM_IDLECT2 REG16(CLKRST_BASE_ADDR+0x08)
#define CLKRST_ARM_IDLECT2_EN_LBFREECK_POS 10
#define CLKRST_ARM_IDLECT2_EN_LBFREECK_NUMB 1
#define CLKRST_ARM_IDLECT2_EN_LBFREECK_RES_VAL 0x0
//R/W
#define CLKRST_ARM_IDLECT2_EN_GPIOCK_POS 9
#define CLKRST_ARM_IDLECT2_EN_GPIOCK_NUMB 1
#define CLKRST_ARM_IDLECT2_EN_GPIOCK_RES_VAL 0x0
//R/W
#define CLKRST_ARM_IDLECT2_DMACK_REQ_POS 8
#define CLKRST_ARM_IDLECT2_DMACK_REQ_NUMB 1
#define CLKRST_ARM_IDLECT2_DMACK_REQ_RES_VAL 0x1
//R/W
#define CLKRST_ARM_IDLECT2_EN_TIMCK_POS 7
#define CLKRST_ARM_IDLECT2_EN_TIMCK_NUMB 1
#define CLKRST_ARM_IDLECT2_EN_TIMCK_RES_VAL 0X0
//R/W
#define CLKRST_ARM_IDLECT2_EN_APICK_POS 6
#define CLKRST_ARM_IDLECT2_EN_APICK_NUMB 1
#define CLKRST_ARM_IDLECT2_EN_APICK_RES_VAL 0x0
//R/W
#define CLKRST_ARM_IDLECT2_EN_HSABCK_POS 5
#define CLKRST_ARM_IDLECT2_EN_HSABCK_NUMB 1
#define CLKRST_ARM_IDLECT2_EN_HSABCK_RES_VAL 0X0
//R/W
#define CLKRST_ARM_IDLECT2_EN_LBCK_POS 4
#define CLKRST_ARM_IDLECT2_EN_LBCK_NUMB 1
#define CLKRST_ARM_IDLECT2_EN_LBCK_RES_VAL 0X0
//R/W
#define CLKRST_ARM_IDLECT2_EN_LCDCK_POS 3
#define CLKRST_ARM_IDLECT2_EN_LCDCK_NUMB 1
#define CLKRST_ARM_IDLECT2_EN_LCDCK_RES_VAL 0x0
//R/W
#define CLKRST_ARM_IDLECT2_EN_PERCK_POS 2
#define CLKRST_ARM_IDLECT2_EN_PERCK_NUMB 1
#define CLKRST_ARM_IDLECT2_EN_PERCK_RES_VAL 0x0
//R/W
#define CLKRST_ARM_IDLECT2_EN_XORPCK_POS 1
#define CLKRST_ARM_IDLECT2_EN_XORPCK_NUMB 1
#define CLKRST_ARM_IDLECT2_EN_XORPCK_RES_VAL 0x0
//R/W
#define CLKRST_ARM_IDLECT2_EN_WDTCK_POS 0
#define CLKRST_ARM_IDLECT2_EN_WDTCK_NUMB 1
#define CLKRST_ARM_IDLECT2_EN_WDTCK_RES_VAL 0x0
//R/W
//CLKRST_ARM_EWUPCT
//-------------------
#define CLKRST_ARM_EWUPCT REG16(CLKRST_BASE_ADDR+0x0C)
#define CLKRST_ARM_EWUPCT_REPWR_EN_POS 5
#define CLKRST_ARM_EWUPCT_REPWR_EN_NUMB 1
#define CLKRST_ARM_EWUPCT_REPWR_EN_RES_VAL 0x1
//R/W
#define CLKRST_ARM_EWUPCT_EXTPW_POS 0
#define CLKRST_ARM_EWUPCT_EXTPW_NUMB 5
#define CLKRST_ARM_EWUPCT_EXTPW_RES_VAL 0xF
//R/W
//CLKRST_ARM_RSTCT1
//-------------------
#define CLKRST_ARM_RSTCT1 REG16(CLKRST_BASE_ADDR+0x10)
#define CLKRST_ARM_RSTCT1_SW_RST_POS 3
#define CLKRST_ARM_RSTCT1_SW_RST_NUMB 1
#define CLKRST_ARM_RSTCT1_SW_RST_RES_VAL 0x0
//R/W
#define CLKRST_ARM_RSTCT1_DSP_RST_POS 2
#define CLKRST_ARM_RSTCT1_DSP_RST_NUMB 1
#define CLKRST_ARM_RSTCT1_DSP_RST_RES_VAL 0x0
//R/W
#define CLKRST_ARM_RSTCT1_DSP_EN_POS 1
#define CLKRST_ARM_RSTCT1_DSP_EN_NUMB 1
#define CLKRST_ARM_RSTCT1_DSP_EN_RES_VAL 0x0
//R/W
#define CLKRST_ARM_RSTCT1_ARM_RST_POS 0
#define CLKRST_ARM_RSTCT1_ARM_RST_NUMB 1
#define CLKRST_ARM_RSTCT1_ARM_RST_RES_VAL 0x0
//R/W
//CLKRST_ARM_RSTCT2
//-------------------
#define CLKRST_ARM_RSTCT2 REG16(CLKRST_BASE_ADDR+0x14)
#define CLKRST_ARM_RSTCT2_PER_EN_POS 0
#define CLKRST_ARM_RSTCT2_PER_EN_NUMB 1
#define CLKRST_ARM_RSTCT2_PER_EN_RES_VAL 0x0
//R/W
//CLKRST_ARM_SYSST
//-------------------
#define CLKRST_ARM_SYSST REG16(CLKRST_BASE_ADDR+0x18)
#define CLKRST_ARM_SYSST_CLOCK_SELECT_POS 11
#define CLKRST_ARM_SYSST_CLOCK_SELECT_NUMB 3
#define CLKRST_ARM_SYSST_CLOCK_SELECT_RES_VAL 0x0
//R/W
#define CLKRST_ARM_SYSST_IDLE_DSP_POS 6
#define CLKRST_ARM_SYSST_IDLE_DSP_NUMB 1
#define CLKRST_ARM_SYSST_IDLE_DSP_RES_VAL 0x0
//R
#define CLKRST_ARM_SYSST_POR_POS 5
#define CLKRST_ARM_SYSST_POR_NUMB 1
#define CLKRST_ARM_SYSST_POR_RES_VAL 0X0
//R/C
#define CLKRST_ARM_SYSST_EXT_RST_POS 4
#define CLKRST_ARM_SYSST_EXT_RST_NUMB 1
#define CLKRST_ARM_SYSST_EXT_RST_RES_VAL 0x0
//R/C
#define CLKRST_ARM_SYSST_ARM_MCRST_POS 3
#define CLKRST_ARM_SYSST_ARM_MCRST_NUMB 1
#define CLKRST_ARM_SYSST_ARM_MCRST_RES_VAL 0x0
//R/C
#define CLKRST_ARM_SYSST_ARM_WDRST_POS 2
#define CLKRST_ARM_SYSST_ARM_WDRST_NUMB 1
#define CLKRST_ARM_SYSST_ARM_WDRST_RES_VAL 0x0
//R/C
#define CLKRST_ARM_SYSST_GLOB_SWRST_POS 1
#define CLKRST_ARM_SYSST_GLOB_SWRST_NUMB 1
#define CLKRST_ARM_SYSST_GLOB_SWRST_RES_VAL 0x0
//R/C
#define CLKRST_ARM_SYSST_DSP_WDRST_POS 0
#define CLKRST_ARM_SYSST_DSP_WDRST_NUMB 1
#define CLKRST_ARM_SYSST_DSP_WDRST_RES_VAL 0x0
//R/C
//CLKRST_ARM_CKOUT1
//-------------------
#define CLKRST_ARM_CKOUT1 REG16(CLKRST_BASE_ADDR+0x1C)
#define CLKRST_ARM_CKOUT1_TCLKOUT_POS 4
#define CLKRST_ARM_CKOUT1_TCLKOUT_NUMB 2
#define CLKRST_ARM_CKOUT1_TCLKOUT_RES_VAL 0x1
//R/W
#define CLKRST_ARM_CKOUT1_DCLKOUT_POS 2
#define CLKRST_ARM_CKOUT1_DCLKOUT_NUMB 2
#define CLKRST_ARM_CKOUT1_DCLKOUT_RES_VAL 0x1
//R/W
#define CLKRST_ARM_CKOUT1_ACLKOUT_POS 0
#define CLKRST_ARM_CKOUT1_ACLKOUT_NUMB 2
#define CLKRST_ARM_CKOUT1_ACLKOUT_RES_VAL 0X1
//R/W
//CLKRST_ARM_CKOUT2
//-------------------
#define CLKRST_ARM_CKOUT2 REG16(CLKRST_BASE_ADDR+0x20)
//R/W
//-------------------------------------------------------------------------------
//
// DSP REGISTERS DECLARATION
//
//-------------------------------------------------------------------------------
#define DSPCLKM_BASE_ADDR MEM_DSP_CLKM_ADDR
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