📄 armperipherals.h
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10: CLKOUT = CLKREF/4
11: CLKOUT = CLKREF/4
*/
#define BREAKLN 1 /* Readonly. 0 indicates that the DPLL has broken lock for some unknown reason.
When the lock condition is restored or the control register is written, returns to 1. */
#define LOCK 0 /* Readonly. 1 indicates the DPLL is in the LOCK mode and CLKOUT is the desired synthesized
clock frequency.
0 indicates the DPLL is in the BYPASS mode and CLKOUT contains a divided-down output clock. */
struct ULPD_register_set_struct {
volatile unsigned int counter32lo; /* Readonly. Lower 16 bits of the number of ticks from the 32KHz clock
during gauging time. */
volatile unsigned int counter32hi; /* Readonly. Upper 16 bits of the number of ticks from the 32KHz clock
during gauging time. */
volatile unsigned int counter_high_FREQlo; /* Readonly. Lower 16 bits of the number of ticks from the high frequency clock
during gauging time. */
volatile unsigned int counter_high_FREQhi; /* Readonly. Upper 16 bits of the number of ticks from the high frequency clock
during gauging time. */
volatile unsigned int gauging_CTL; /* Drives the gauging functionality.
Bit 1 selects 12MHz clock for high frequency clock when 0. 1 reserved.
Bit 0 starts the gauging when 1, stops it when 0. */
volatile unsigned int gauging_status; /* Gives the status of the gauging functionality.
Bit 2 indicates a 32KHz clock overflow when 1.
Bit 1 indicates a high frequency clock overflow when 1.\
Bit 0 indicates an interrupt occurs from gauging. */
volatile unsigned int reserved0;
volatile unsigned int reserved1;
volatile unsigned int reserved2;
volatile unsigned int reserved3;
volatile unsigned int reserved4;
volatile unsigned int setup_analog_cell3_ULPD1; /* Number of 32KHz clock to wake up. */
volatile unsigned int clock_ctl; /* Manage clock output and inactive values.
Bit 4 enables USB_CLK0 when 1.
Bit 2 indicates the status of inactive BT_MCLK_OUT .
Bit 1 indicates the status of inactive COM_MCLK_OUT.
Bit 0 enables 32KHz on UART clock when 1. */
volatile unsigned int soft_REQ; /* Manage software clock requests.
Bit 3 requests clocking on USB_CLK0.
Bit 2 requests clocking on BT_MCLK_OUT.
Bit 1 requests clocking on COM_MCLK_OUT.
Bit 0 requests clocking on 48MHz DPLL. */
volatile unsigned int counter32_FIQ; /* Number of 32KHz clocks to delay active modem shutdown
signal after receiving an active EXT_FIQ signal. */
volatile unsigned int DPLL_CTL; /* Manages 48MHz DPLL. Bit definitions same as the general DPLLs. */
volatile unsigned int status_REQ; /* Indicates the status of hardware requests. */
};
/* } *pULPD_RS = (struct ULPD_register_set_struct*)0xFFFE0800; */
/* Bluetooth UART on the front panel: Pin2pin mapping
* D9 socket OMAP1509 pins
*11 DCD_SUBD2 <- (U29MAX562)->BT_UART_DCD<-U8BFPGA
*11 DSR_SUBD2 <- (U29MAX562)->BT_UART_DSR<-U8BFPGA
*18 RX_SUBD2 -> (U29MAX562)->BT_UART_RXD->JP51:2-3->U23LineDriver->H12-13->1509.rx1/debug_2
*18 RTS_SUBD2 <- (U29MAX562)<-BT_UART_RTSZ<-U23LineDriver<-H15-9<-1509.rts1
*18 TX_SUBD2 <- (U29MAX562)<-BT_UART_TXD<-JP52:2-3<-U23LineDriver<-H14-14<-1509.tx1
*18 CTS_SUBD2 -> (U29MAX562)->BT_UART_CTSZ->U23LineDriver->H16-14->1509.cts1/debug_3
*13 DTR_SUBD2 <- (U29MAX562)<-BT_UART_DTR<-H13-21<-1509.wire_sdo/dtr/dtr/Gated1
*11 RI_SUBD2 -> (U29MAX562)->BT_UART_RI->U8BFPGA
*/
struct UART_struct {
volatile unsigned char RHR_THR_DLL; /* */
volatile unsigned char reserved0[3];
volatile unsigned char IER_DLH;
volatile unsigned char reserved1[3];
volatile unsigned char IIR_FCR_EFR;
volatile unsigned char reserved2[3];
volatile unsigned char LCR;
volatile unsigned char reserved3[3];
volatile unsigned char MCR;
volatile unsigned char reserved4[3];
volatile unsigned char LSR; /* Readonly. */
volatile unsigned char reserved5[3];
volatile unsigned char MSR_TCR;
volatile unsigned char reserved6[3];
volatile unsigned char SPR_TLR;
volatile unsigned char reserved7[3];
volatile unsigned char MDR1;
volatile unsigned char reserved8[3];
volatile unsigned char reserved9[0x34-0x24+4];
volatile unsigned char UASR;
volatile unsigned char reserved10[3];
volatile unsigned char SCR;
volatile unsigned char reserved11[3];
volatile unsigned char SSR; /* Readonly. */
volatile unsigned char reserved12[3];
volatile unsigned char OSC_12M_SEL;
volatile unsigned char reserved13[3];
};
/*
*pUART1 = (struct UART_struct*)0xFFFB0000,
*pUART2 = (struct UART_struct*)0xFFFB0800;
*/
/* Modem UART on the front panel: Pin2pin mapping
1510.tx/pwt->J20-8->H20-8->GP_UART_TX<<JP25: 1-2>>UART_TX->U28(MAX562)->TX_IN
1510.rx/pwl->J21-6->H21-6->GP_UART_RX<<JP27: 1-2>>UART_RX<-U28(MAX562)<-RX_IN
1510.bt_mclk_req/cts3<-J16-12<-H16-12<-GP_UART_CTS<<JP21:1-2>>UART_CTS<-U28(MAX562)<-CTS_IN
1510.bt_mclk_out/rts3->J14-13->H14-13->GP_UART_RTS<<JP23:1-2>>UART_RTS->U28(MAX562)->RTS_IN
1510.wire_sdo/dcd/dcd1->J13-21->H13-21->UART_DTR->U28(MAX562)->DTR_IN
1510.wire_sdi/dsr<-J20-13<-H20-13<-UART_DSR<-U28(MAX562)<-DSR_IN
FPGA.UART_DCD<-U28(MAX562)<-DCD_IN
FPGA.UART_RI<-U28(MAX562)<-RI_IN
*/
typedef volatile unsigned char UIR_UART;
// volatile unsigned char* pUIR_UART3 = (unsigned char*)0xFFFCEFFC;
#define UART_MASK_IT 1 /* Mask UART interrupt. */
#define UART_ACCESS 0 /* 0: UART3 registers accessible by the MPU TIPB.
1: UART3 registers accessible by the DSP shared TIPB. */
struct UART3_struct {
volatile unsigned char RHR_THR; /* T/X FIFO mapping */
volatile unsigned char IER;
volatile unsigned char IIR_FCR; /* Writing: */
volatile unsigned char LCR;
volatile unsigned char MCR;
volatile unsigned char LSR; /* Readonly. */
volatile unsigned char MSR_TCR;
volatile unsigned char SPR_TLR;
volatile unsigned char MDR1;
volatile unsigned char reserved0;
volatile unsigned char reserved1;
volatile unsigned char reserved2;
volatile unsigned char reserved3;
volatile unsigned char reserved4;
volatile unsigned char reserved5;
volatile unsigned char reserved6;
volatile unsigned char SCR;
volatile unsigned char SSR; /* Readonly. */
};
//} *pUART3 = (struct UART3_struct*)0xFFFCE800,
// *pUART3_API = (struct UART3_struct*)0xE101E800;
typedef unsigned int MultiplexPinControl;
//#define FUNC_MUX_CTRL_0 (*(unsigned int*)0xFFFE1000)
#define GP_UART_GATING 26 /* 0: tx pin <= 0;
1: tx pin <= general purpose UART(UART3) tx pin. */
#define UWIRE_DCD 16 /* Bit16-17 00: pin uwire_sdo <= uwire serial data output, output;
01: pin uwire_sdo <= DCD UART general purpose, output
10: pin uwire_sdo <= DCD UART bluetooth, output;
11: reserved, output. */
#define BLUETOOTH_MCK_UART3_RTS 9 /* 0: pin bt_mclk_out <= bt_mclk_out, output;
1: pin bt_mclk_out <= UART3 rts, output. */
#define GIGACELL_UART 5 /* 0: pin tx <= general purpose UART tx, output;
pin rx <= hiZ, input;
1: pin tx <= pwt, output;
pin rx <= pwl, output. */
//#define FUNC_MUX_CTRL_1 (*(unsigned int*)0xFFFE1004)
//#define FUNC_MUX_CTRL_2 (*(unsigned int*)0xFFFE1008)
struct timer_CTL_struct {
volatile unsigned int CNTL_TIMER; /* Control timer. */
#define SOFT 0x7 /* 0: The periperal halts immediately, either retaining
or discarding the current state, when a break point
is encountered;
1: The peripheral stops after completion of the current
task when a break point is encountered. */
#define FREECLOCK 0x6 /* 0: SOFT bit selects the emulation mode;
1: Peripheral clock runs free regardless of the SOFT bit. */
#define CLOCK_ENABLE 0x5 /* External timer clock enable. */
#define TIMERPRESCALER 0x2 /* Bit2-4 Prescaler clock timer value. Division value is
(PTV + 1)th power of 2. */
#define AUTORELOAD 0x1 /* 0: One-shot timer;
1: Autoreload timer. */
#define STARTCLOCK 0x0 /* 0: Stop timer;
1: Start timer. */
volatile unsigned int LOAD_TIM; /* Load timer. */
volatile unsigned int READ_TIM; /* Read timer. */
};
struct interrupt_handler_struct {
volatile unsigned int ITR; /* Interrupt input register. */
volatile unsigned int MIR; /* Mask interrupt register. */
volatile unsigned int reserved0[0x10/4 - 0x04/4 - 1];
volatile unsigned int SIR_IRQ_CODE; /* IRQ encoded source register. */
volatile unsigned int SIR_FIQ_CODE; /* FIQ encoded source register. */
volatile unsigned int CONTROL_REG; /* Interrupt control register. */
#define NEW_IRQ_AGR 0x0
#define NEW_FIQ_AGR 0x1
volatile unsigned int ILR[32]; /* Priority level for IRQ */
#define PRIORITY 0x2 /* Bit2-6 set priority level when the interrupt is routed to IRQ or FIQ */
#define TRIGGER_TYPE 0x1 /* Bit 1 sets the trigger type. */
#define EDGE_TRIGGER 0x0
#define LEVEL_TRIGGER 0x1
#define TRIGGER_ROUTE 0x0 /* Bit 0 sets where to send the action. */
#define IRQ_ROUTE 0x0
#define FIQ_ROUTE 0x1
volatile unsigned int ISR; /* Software interrupt set register */
};
#define IRQ_TIMER3 48
#define IRQ_TIMER3_TRIGGER_TYPE EDGE_TRIGGER
#define IRQ_UART1 14
#define IRQ_UART1_TRIGGER_TYPE EDGE_TRIGGER
#define IRQ_GPIO 46
#define IRQ_GPIO_TRIGGER_TYPE LEVEL_TRIGGER
struct GPIO_struct {
volatile unsigned short data_input_reg; /* Data input register */
volatile unsigned short reserved0;
volatile unsigned short data_output_reg; /* Data output register */
volatile unsigned short reserved1;
volatile unsigned short direction_control_reg; /* Direction control register */
#define GPIO_DIRECTION_INPUT 1
#define GPIO_DIRECTION_OUTPUT 0
volatile unsigned short reserved2;
volatile unsigned short interrupt_control_reg; /* Interrupt control register */
#define GPIO_INTERRUPT_LOW2HIGH 1
#define GPIO_INTERRUPT_HIGH2LOW 0
volatile unsigned short reserved3;
volatile unsigned short interrupt_mask_reg; /* Interrupt mask register */
#define GPIO_INTERRUPT_DISABLE 1
#define GPIO_INTERRUPT_ENABLE 0
volatile unsigned short reserved4;
volatile unsigned short interrupt_status_reg; /* Interrup status register */
#define GPIO_INTERRUPT_OCCURRED 1
volatile unsigned short reserved5;
volatile unsigned short pin_control_reg; /* Pin control register, only for ARM */
#define GPIO_PIN4ARM 1
#define GPIO_PIN4DSP 0
volatile unsigned short reserved6;
};
enum GPIO_interrupt_type { NON_INTERRUPT, HIGH2LOW_INTERRUPT, LOW2HIGH_INTERRUPT };
#define GPIO_BASE_ADDRESS 0xFFFCE000
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