armperipherals.h

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	volatile unsigned short arm_ewupct;
	volatile unsigned short reserved3;
	volatile unsigned short arm_rstct1;
	volatile unsigned short reserved4;
	volatile unsigned short arm_rstct2;
	volatile unsigned short reserved5;
	volatile unsigned short arm_sysst;
	volatile unsigned short reserved6;
	volatile unsigned short reserved7;
	volatile unsigned short reserved8;
	volatile unsigned short reserved9;
	volatile unsigned short reserved10;
};

/* The bit assignments of the MPU clock control register ARM_CKCTL */
#define ARM_INTHCK_SEL 14 /* Controls which clock is used for MPU interrupt handler. */
#define EN_DSPCK 13 /* Enables the DSP clock to be turned on during the reset state. */
#define ARM_TIMXO 12 /* Select MPU internal timers clock--0:CLK_IN, 1:CK_GEN1.		 */
#define DSPMMUDIV 10 /* Set the prescaler for the DSPMMU clock subdomain clock.		 */
#define TCDIV 8		/* Set the prescaler for the TC clock domain clock.				 */
#define DSPDIV 6	/* Set the prescaler for the DSP clock domain clock. 			 */
#define ARMDIV 4	/* Set the prescaler for the MPU clock domain clock.			 */
#define LCDDIV 2	/* Set the prescaler for the LCD controller clock signal.		 */
#define PERDIV 0	/* Set the prescaler for the MPU peripheral clock subdomain clock. */
/*
	NOTE1: In fully synchronous mode, ARMDIV, DSPDIV, DSPMMUDIV, and TCDIV must be the same.
	NOTE2: DSPMMU_CK = DSP_CK, or DSPMMU_CK = DSP_CK/2.
	NOTE3: In synchronous scalable mode, DSPMMUDIV and ARMDIV >= TCDIV  ??
	NOTE4: The maximum speed of DSP MMU is limited to 85MHz. */
/************************************************************************************/
/* DIV prescaler value table														*/
#define DIV1 0x00
#define DIV2 0x01
#define DIV4 0x10
#define DIV8 0x11
/* 00 -- 1
   01 -- 2
   10 -- 4
   11 -- 8
   			*/      


/* The bit assignments of the MPU idle mode entry 1 register ARM_IDLECT1 */
#define SETARM_IDLE 11 /* 1: Initiates the MPU idle mode. */
#define WKUP_MODE	10 /* 0: The MPU idle mode is exited upon a low level at the CHIP_nWAKEUP pin
							 	after the interrupt has been asserted.
						  	  Also any wake-up condition wakes up the 1510 device out of CHIP_IDLE
						  	  only if the CHIP_nWAKEUP is active. 			
						  1: The MPU idle mode is exited after the interrupt has been asserted regardless
						  		of the CHIP_nWAKEUP status.
						  0: Also any wake-up condition wakes up the 1510 device out of CHIP_IDLE
						  		regardless of the CHIP_nWAKEUP status. */
#define IDLTIM_ARM	9 /* 0: The MPU internal timers remains active when the MPU enters the idle mode.
						 1: The timers clock is stopped in conjunction with the MPU clock when the idle
						 	 mode is entered. */
#define IDLAPI_ARM	8 /* 0: The clock supplied to the MPUI remains active when the DSP enters the idle
							 mode( DSP_CK stopped ).
					     1: Reserved. To stop the MPUI clock, set ARM_IDLECT2.EN_APICK to 0. */
#define IDLDPLL_ARM	7 /* When all the following apply:
							1, The DSP is in global-idle mode;
							2, MPU is set in idle mode( either from request or wait-for-interrupt );
							3, No active DMA transaction or TCLB_EN signal is inactive;
							4, No peripheral bus posted write is queued;
							5, The peripheral clocks are stopped.
						then 1: The DPLL1,2,3 macros enter idle mode;
							 0: The DPLL1,2,3 macros remain active.							*/
#define IDLIF_ARM 6	/* 0: The clocks TIPB_CKs, DMA_CK and TC_CK remain active when the MPU enters the idle mode;
					   1: The clocks TIPB_CKs, DMA_CK and TC_CK are stopped in conjunction with the MPU clock
					   		when the idle mode is entered.
					   	NOTE1: These clocks are stopped with the assumption that there is no DMA transaction.
					   	NOTE2: TC_CK is stopped only is the DSP system is already in an idle mode.	
					   		 */
#define IDLHSAB_ARM 5 /* 0: The clock supplied to the high speed access bus remains active when the MPU
							 enters the idle mode;
					     1: Reserved. To disable the HSAB_CK, set ARM_IDLECT2.EN_HSABCK to 0. */
#define IDLLB_ARM	4 /* 0: The clock supplied to the local bus remains active when the MPU	enters the 
								idle mode;
						 1: Reserved. To disable the LB_CK, set ARM_IDLECT2.EN_LBCK to 0. */
#define IDLLCD_ARM	3 /* 0: The clock supplied to the LCD controller remains active then the MPU enters 
							 the idle mode;
						 1: Reserved. To disable the LCD_CK clock, set the ARM_IDLECT2.EN_LCDCK to 0. */
#define IDLPER_ARM	2 /* 0: The ARMPER_CK remains actvie then the MPU enters the idle mode.
						 1: The ARMPER_CK clock is stopped in conjunction with the MPU idle mode entry.*/
#define IDLXORP_ARM 1 /* 0: The OS timer(watchdog timer, CLK_IN/14) and the ARMXOR_CK clock(buffered CLK_IN) remain active when the MPU enters the 
								idle mode;
						 1: The OS timer and the ARMXOR_CK clock are stopped in conjunction with the entry
						     of the MPU idle mode. */
#define IDLWDT_ARM	0 /* 0: The clock supplied to the internal timer/watchdog remains active when the MPU
								enters the idle mode;
						 1: The clock supplied to the internal timer/watchdog is stopped in conjunction with
						 	    the MPU idle mode entry.
						 NOTE: When the internal timer/watchdog is configured as watchdog timer, the clock is 
						 			never shutdown, regardless of the value of the IDLWDT_ARM bit. */

/* The bit assignments of the MPU idle mode entry 2 register ARM_IDLECT2  */
#define EN_LBFREECK 10 /* 0: The LBFREE_CK clock( generating the local bus external output clock ) is stoped.
						  1: The LBFREE_CK clock is active */
#define EN_GPIOCK	9  /* 0: The clock of the MPU GPIO connected to the MPU TIPB is stopped;
						  1: The clock is active.	*/
#define DMACK_REQ	8  /* 0: The DMA clock is stopped only when the idle mode is entered if ARM_IDLECT1.IDLIF_ARM is 1;
						  1: The DMA clock is stopped by default; It is reactivated upon DMA requests only. */
#define EN_TIMCK	7  /* 0: The clock of the internal timers connected to the MPU TIPB is stopped;
						  1: The clock is  active( Can be stopped with the entry of MPU idle mode depending
						  		on the ARM_IDLECT1.IDLETIM_ARM bit.	*/
#define EN_APICK	6  /* 0: The MPUI clock is stopped;	
						  1: The MPUI clock is active. */
#define EN_HSABCK	5  /* 0: The high speed access bus is stopped;
						  1: The high speed access bus is active. */
#define EN_LBCK		4  /* 0: The local bus clock is stopped;
						  1: Teh local bus closk is active.			 */
#define EN_LCDCK	3  /* 0: The LCD clock is stoppped;
						  1: The LCD clock is active.			    */
#define EN_PERCK	2  /* 0: The ARMPER_CK is stopped;
						  1: The ARMPER_CK is active( still can be stopped depending on 
						  		ARM_IDLECT1.IDLLRP_ARM bit status. */
#define EN_XORPCK	1  /* 0: The clock of the OS timer connected to the MPU TIPB and the CLK_IN reference clock
								are stopped;
						  1: The OS timer clock( CLK_IN/14 ) and the CLK_IN reference clock( XORP_CK ) are active( still can\
						  		be stopped depending on the stauts of ARM_IDLECT1.IDLXORP_ARM bit. */
#define EN_WDTCK	0  /* 0: The timer/watchdog clock is stopped;
						  1: The timer/watchdog clock is active( still can be stopped depending on the status
						  		of ARM_IDLECT1.IDLWDT_ARM bit.
						 NOTE: When the internal timer/watchdog is configured as watchdog timer, the clock is 
						 			never shutdown, regardless of the value of this bit. */


						  		
/* The bit assignments of the MPU external wake-up register ARM_EWUPCT */
#define REPWR_EN	5 /* 0: The NFRP pin is set to logic low when the traffic controller is in idle mode;
						 1: The NFRP pin is not activated when the TC idle mode is entered.	*/
#define EXTPW		0 /* The 5 bits define the delay from the nRESPWRON pin going high to the clocks restarting.*/						 


/* The bit assignments of the MPU reset control 1 register ARM_RSTCT1 */
#define SW_RST		3 /* 0: The DSP, the MPU and the peripheral clock domain are enbaled.
						 1: Resets the DSP, MPU and peripherals. Once set to logic 1 by the MPU, this bit
						 		returns to logic 0 once the reset completes. */
#define DSP_RST		2 /* 0: The priority, the EMIF configuration registers and the MPUI are reset.
						 1: The priority and the EMIF configuration registers can be programmed. */		
#define DSP_EN		1 /* 0: Resets the DSP, excluding the configuration setting, and maintains the reset
							state as long as this bit is asserted low;
						 1: The DSP is enabled. After a glabal reset, this bit must be set to a logical 1
						 		in order to enbale the DSP. */
#define ARM_RST		0 /* 0: The MPU clock domain is enabled;
						 1: Reset the MPU. Once set to logical 1 by the MPU, this bit returns to logic 0
						 	 on the next cycles.
						 NOTE: Writing 0 to  DSP_EN bit and 1 to ARM_RST bit together initiate a global 
						 	software reset. */	 						 			
                                                                       
/* The bit assigments of the MPU reset control 2 register ARM_RSTCT2 */
#define PER_EN 0	/* 0: Writing a logical 0 sets the ARMPER_nRST signal to be active;
					   1: Writing a logical 1 sets the ARMPER_nRST signal to be inactive. */
					   
        
/* The bit assigments of the MPU system status register ARM_SYSST */
#define CLOCK_SELECT 11 /* The three bits set and show the 1510 device clock scheme.*/
#define FULLYSYNCHRONOUS 0x00
#define SYNCHRONOUSSCALABLE 0x02
#define BYPASS 0x05
#define MIXMODE3 0x06
/*
	000 Fully synchronous(V)
	001 Fully asynchronous(X)
	010 Synchronous scalable(V)
	011 Mix mode #1, MPU synchronous to TC, while DSP MMU asynchronous to them(X)
	100 MIX mode #2, DSP MMU synchronous to TC, while MPU asynchronous to them(X)
	101 Bypass(V)
	110 Mix mode #3, MPU synchronous to TC, DSP MMU synchronous scalable to them(V)
	111 Mix mode #4, DSP MMU synchronous to TC, MPU synchronous scalable to them(X)
	*/
#define IDLE_DSP	6 /* Readonly bit.
						0: The DSP is active;
						1: The DSP is in global-idle state. */
#define POR			5 /* Read/clear-only bit.
						0: No power-on reset has been detected.
						1: A power-on reset has occurred. */
/*fine EXT_RST		4 //Read/clear-only bit.
						0: No external reset detected.
						1: An external reset has been asserted. */
#define ARM_MCRST	3 /* Read/clear-only bit.
						0: The MPU has not been reset.
						1: The MPU has been reset. */
#define ARM_WDRST	2 /* Read/clear-only bit.
						0: MPU timer/watchdog underflow has not occurred.
						1: MPU timer/watchdog underflow has generated the reset. */
#define GLOB_SWRST	1 /* Read/clear-only bit.
						0: A global software reset has not been requested.
						1: A global software reset has been requested. */
#define DSP_WDRST	0 /* Read/clear-only bit.
						0: DSP timer/watchdog underflow has not occurred.
						1: DSP timer/watchdog underflow has generated the reset. */

#if 1
/* DSP peripherals accessed through MPUI interface. */
struct DSP_CLK_reset_power_CTL_struct {
	volatile unsigned short DSP_CKCTL;
	volatile unsigned short DSP_IDLECT1;
	volatile unsigned short DSP_IDLECT2;
	volatile unsigned short Reserved0;
	volatile unsigned short Reserved1;
	volatile unsigned short DSP_RSTCT2;
	volatile unsigned short DSP_SYSST;
	volatile unsigned short Reserved2;
	volatile unsigned short Reserved3;
};
/*
 * NOTE: The maximum speed of the UART(Only UART3?) is limited to 50MHz.
 */
//} *pDSP_CRPC = (struct DSP_CLK_reset_power_CTL_struct*)0xE1008000;
#endif
typedef unsigned int DPLL_CONTROL;
/* unsigned int *pDPLL1_CTL = (unsigned int *)0xFFFECF00;
unsigned int *pDPLL2_CTL = (unsigned int *)0xFFFED000;
unsigned int *pDPLL3_CTL = (unsigned int *)0xFFFED100; */

/* The bit assigments of the DPLL control register */
#define IOB 13		/* 0: The DPLL continues to output the synthesized clock
								even if the DPLL core indicates that it has lost the lock, but BREAKLN is active low.
                       1: The DPLL switches to bypass mode and starts a new locking sequence if the DPLL core indicates
                       			that it has lost the lock. */
#define PLL_MULT 7	/* Bit 7-11 The DPLL multiply value. */
#define PLL_DIV 5	/* Bit 5-6  The DPLL divide value.
						00: CLKOUT = CLKREF
						01: CLKOUT = CLKREF/2
						10: CLKOUT = CLKREF/3
						11: CLKOUT = CLKREF/4 
							*/               
/* 
	NOTE: When PLL_MUL is 0 or 1, the CLKOUT is not synthesized by the DPLL, but simply a divided value of CLKREF.
*/
#define PLL_ENABLE 4 /* 0: Clearing this bit causes the DPLL to switch back to bypass mode.
						1: Setting this bit requests the DPLL to enter the LOCK mode. */
#define BYPASS_DIV 2 /* Bit 2-3 Determines the CLKOUT frequency when in bypass mode.
							00: CLKOUT = CLKREF
							01: CLKOUT = CLKREF/2