📄 armperipherals.h
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/****************************************************************************
OMAP1510DC EVM Building project
Oct 3, 2001 China Digipro
File: armperipherals.h
Content: Describes the 1510 peripheral interfaces
Author: Zhu, Yaozong
*****************************************************************************/
struct config_register_set {
volatile unsigned int FUNC_MUX_CTRL_0;
volatile unsigned int FUNC_MUX_CTRL_1;
volatile unsigned int FUNC_MUX_CTRL_2;
volatile unsigned int COMP_MODE_CTRL_0;
volatile unsigned int FUNC_MUX_CTRL_3;
volatile unsigned int FUNC_MUX_CTRL_4;
volatile unsigned int FUNC_MUX_CTRL_5;
volatile unsigned int FUNC_MUX_CTRL_6;
volatile unsigned int FUNC_MUX_CTRL_7;
volatile unsigned int FUNC_MUX_CTRL_8;
volatile unsigned int FUNC_MUX_CTRL_9;
volatile unsigned int FUNC_MUX_CTRL_A;
volatile unsigned int FUNC_MUX_CTRL_B;
volatile unsigned int FUNC_MUX_CTRL_C;
volatile unsigned int FUNC_MUX_CTRL_D;
volatile unsigned int PULL_DWN_CTRL_0;
volatile unsigned int PULL_DWN_CTRL_1;
volatile unsigned int PULL_DWN_CTRL_2;
volatile unsigned int PULL_DWN_CTRL_3;
volatile unsigned int GATE_INH_CTRL_0;
volatile unsigned int VOLTAGE_CTRL_0;
volatile unsigned int TEST_DBG_CTRL_0;
volatile unsigned int MOD_CONF_CTRL_0;
};
#define CONFIGURATION_BASE 0xFFFE1000
#define OMAP1510_COMPATIBLE_PATTERN 0x0000EAEF
/* FUNC_MUX_CTRL_0 Bit definitions */
/* The two TI peripheral bridges interface. */
struct MPU_TIPB_struct {
volatile unsigned short TIPB_CNTL;
volatile unsigned short reserved0;
volatile unsigned short TIPBBUS_ALLOC;
volatile unsigned short reserved1;
volatile unsigned short MPU_TIPB_CNTL;
volatile unsigned short reserved2;
volatile unsigned short ENHANCED_TIPB_CNTL;
volatile unsigned short reserved3;
volatile unsigned short ADDRESS_DBG; /* Readonly. */
volatile unsigned short reserved4;
volatile unsigned short DATA_DEBUG_LOW; /* Readonly. */
volatile unsigned short reserved5;
volatile unsigned short DATA_DEBUG_HIGH; /* Readonly. */
volatile unsigned short reserved6;
volatile unsigned char DEBUG_CNTR_SIG; /* Readonly. */
};
//} *pMPU_TIPB1 = (struct MPU_TIPB_struct*)0xFFFECA00,
// *pMPU_TIPB2 = (struct MPU_TIPB_struct*)0xFFFED300;
/* The MPUI interface register set is located at MPU TIPB private peripheral strobe 1. */
struct MPUI_struct {
volatile unsigned int CTRL_REG; /* Control register */
volatile unsigned int DEBUG_ADDR; /* Readonly. Contains the address from the last operation in case of an abortion. */
volatile unsigned int DEBUG_DATA; /* Readonly. Contains the data from the last operation in case of an abortion. */
volatile unsigned short DEBUG_FLAG; /* Readonly. Debug flag register. */
volatile unsigned short reserved0;
volatile unsigned short STATUS_REG; /* Readonly. MPUIF status register. */
volatile unsigned short reserved1;
volatile unsigned short DSP_STATUS_REG; /* Readonly. Current status of DSP. */
volatile unsigned short reserved2;
volatile unsigned short DSP_BOOT_CONFIG; /* Boot configuration of DSP. */
volatile unsigned short reserved3;
volatile unsigned short DSP_API_CONFIG; /* MPUI size information. */
volatile unsigned short reserved4;
};
// } *pMPUI = (struct MPUI_struct*)0xFFFEC900;
/* The traffic controller registers are located at MPU private peripheral bus
strobe line 1, starting at 0xFFFECC00. */
struct TC_struct {
volatile unsigned int IMIF_PRIO; /* Give consecutive accesses (set value+1) of internal memory to the masters. */
volatile unsigned int EMIFS_PRIO_REG; /* Give consecutive accesses (set value+1) of external slow memory to the masters. */
volatile unsigned int EMIFF_PRIO_REG; /* Give consecutive accesses (set value+1) of external fast memory to the masters. */
volatile unsigned int EMIFS_CONFIG_REG; /* Slow memory config register. */
volatile unsigned int EMIFS_CS0_CONFIG; /* Slow memory chip-select config registers. */
volatile unsigned int EMIFS_CS1_CONFIG;
volatile unsigned int EMIFS_CS2_CONFIG;
volatile unsigned int EMIFS_CS3_CONFIG;
volatile unsigned int EMIFF_SDRAM_CONFIG;
volatile unsigned int EMIFF_MRS;
volatile unsigned int TIMEOUT1;
volatile unsigned int TIMEOUT2;
volatile unsigned int TIMEOUT3;
volatile unsigned int ENDIANISM;
};
//} *pTC = (struct TC_struct*)0xFFFECC00;
/* Bit mapping for priority registers. */
#define MPU_PRIO 0 /* bit0-1 */
#define DSP_PRIO 4 /* bit4-6 */
#define DMA_PRIO 8 /* bit8-11*/
#define LB_PRIO 12/* bit12-15*/
#define HSAB_PRIO 16 /* bit 16-19 */
/* Bit mapping for slow memory config register. */
#define WP 0 /* Readonly. All flash devices are write-protected. */
#define BM 1 /* Readonly. This bit is sampled from ARM_BOOT pin at reset. CS3 is accessible
at address 0 when this bit is set. */
#define PWD_EN 2 /* Slow memory interface power down enable. */
#define PDE 3 /* Dynamic power down enable for slow memory interface. Clocks are only
active for an active request. */
#define FR 4 /* Readonly. Sampled from the NFRDY pin. Activated by flash devices when
output data invalid. */
/* Bit mapping for slow memory chip-select config registers. */
#define FCLKDIV 0 /* bit0-1 Flash clock divider.
00: divide by 1
01: divide by 2
10: divide by 4
11: divide by 6 */
#define RT 2 /* Determines whether the data coming from the external bus is retimed with CLK. */
#define RDWST 4 /* bit4-7 Number of wait states for asynchronous read operation.
Number of inserted clock cycles in Smart3 protocol.
0-5->1-6 */
#define WRWST 8 /* bit8-11 Numbers of wait states for write operation. */
#define PGWST_WELEN 12 /* bit12-15 For read accesses, number of wait states for page mode ROM reads within a
page. For write accesses, the length of WE pulse duration. */
#define RDMODE 16 /* bit16-18 Read mode select.
000: Asynchronous read
001: Page mode ROM read 4 words per page
010: Page mode ROM read 8 words per page
011: Page mode ROM read 16 words per page
100: Synchronous burst read TI protocol
101: Synchronous burst read Intel Smart3 protocol*/
#define BW 20 /* 0: 16 bit width memory. 1: 32 bit width memory. */
#define FL 21 /* 0: Memory not attached. 1: Memory attached. */
/* Bit mapping for fast memory/SDRAM configuration register. */
#define SLRF 0 /* 1: Places the SDRAM device into self-refresh mode. Mode automatically exited upon access. */
#define SD_RET 1 /* 1: Resynchronization of DRAM returned data needed. Must be 0 for 1510 device. */
#define ARE 2 /* bit2-3 Auto refresh enable. 1: EMIF generates REFR request. 0: Refreshing must be controlled by CPU. */
#define DRAM_TYPE 4 /* bit4-7 Internal DRAM organization. */
#define ARCV 8 /* bit8-23 Autorefresh counter register value. */
#define DRAM_FREQ 24 /* bit24-25 SDRAM frequency range. */
#define PWD 26 /* Power down the SDRAM. */
#define CLK 27 /* Disable SDRAM clock. */
/* Bit mapping for EMIF Fast Interface SDRAM MRS Register. */
#define PGBL 0 /* bit0-2 Page burst length. */
#define SERIAL 3 /* Serial(0) or interleave(1). Must be serial. */
#define CASL 4 /* bit4-6 CAS latency. 1,2 or 3 */
#define WBST 9 /* Write burst must be 0 (burst write same as burst read)? */
/* In synchronous mode, the traffic controller clock must
have the same or a slower frequency as the MPU and the DSPMMU
clock */
/* MPU_SYSST.CLOCK_SELECT(2:0) sets clocking mode of the 1510
device */
/*********************** CLKM1 *******************************************/
/* MPU_CK is set by CLK_GEN1 and ARM_CKCTL.ARMDIV.
IDLE mode of the MPU is controlled by ARM_IDLECT1.SETARM_IDLE */
/* MPU peripheral clocks MPUXOR_CK and ARMPER_CK
MPUXOR_CK, derived from CK_REF is switched by
ARM_IDLECT2.EN_XORPCK, idle mode by ARM_IDLECT1.IDLXORP_ARM
ARMPER_CK, derived from CLK_GEN1/ARM_CKCTL.ARM_PERDIV is switched
by ARM_IDLECT2.EN_PERCK, idle mode by ARM_IDLECT1.IDLPER_ARM */
/* MPU watchdog timer clock, named CK_CLKIN14 or MPUWD_CK is equal to
CK_REF/14. Enabled by ARM_IDLECT2.EN_WDTCK, idle mode controlled by
ARM_IDLECT1.IDLWDT_ARM */
/* MPU internal timers clock MPUTIM_CK is derived either from CLK_IN or
CK_GEN1, which is selected by ARM_CKCTL.ARM_TIMXO.
MPUTIM_CK is enabled by ARM_IDLECT2.EN_TIMCK, idle mode controlled by
ARM_IDLECT1.IDLTIM_ARM. */
/* MPU GPIO clock named MPU_GIO_CLK, is equal to CK_GEN1.\
MPU_GIO_CLK is enabled by ARM_IDLECT2.EN_GPIOCK. */
/*************** PAGE 836 and 837 of 1510 reference manual ************/
/********************* CLKM2 ******************************************/
/* DSP_CK is set by CK_GEN2/ARM_CKCTL.DSPDIV. While DSP is in reset mode,
DSP_CK is enabled by ARM_CKCTL.EN_DSPCK */
/* DSP MMU clock DSPMMU_CK is set by CK_GEN2/ARM_CKCTL.DSPMMUDIV
WARNING! DSPMMU_CK <= 85MHz */
/* DSP interrupt handler clock DSP_INTH_CK is equal to CK_GEN2/2 */
/* DSP UART clock UART_CK is either CK_GEN2/DSP_CKCTL.UARTDIV or CLK_IN,
which is selected by DSP_CKCTL.UARTTXO.
UART_CK is enabled by DSP_IDLECT2.EN_UARTCLK, idle mode controlled by
DSP_IDLECT1.IDLUART_DSP.
WARNING! UART_CK <= 50MHz */
/* DSP GPIO clock DSP_GPIO_CK is either CK_GEN2/DSP_CKCTL.GPIODIV or CLK_IN,
which is selected by DSP_CKCTL.GPIOXO. The clock is enabled by
DSP_IDLECT2.EN_GPIOCLK, idle mode controlled by DSP_IDLECT1.IDLGPIO_DSP. */
/* DSP external peripheral clocks DSPXOR_CK and DSPPER_CK.
DSPXOR_CK is equal to CLK_IN. It is enabled by DSP_IDLECT2.EN_GPIOCK,
idle mode controlled by DSP_IDLECT1.IDLXORP_DSP.
DSPPER_CK is CK_GEN2/DSP_CKCTL.PERDIV. It is enabled by DSP_IDLECT2.EN_PERCK,
idle mode controlled by DSP_IDLECT1.IDLPER_DSP. */
/* DSP watch dog gimer clock DSPWD_CK is CLK_IN/14. It is enabled by
DSP_IDLECT2.EN_WDCLK, idle mode controlled by DSP_IDLECTL1.IDLWDT_DSP. */
/* DSP internal timers clock DSPTIM_CK is either CK_GEN2/2 or CLK_IN, which is
selected by DSP_CKCTL.DSP_TIMXO. It is enabled by DSP_IDLECT2.EN_TIMCLK,
idle mode controlled by DSP_IDLECT1.IDLTIM_DSP. */
/************* PAGE 838 and 839 of 1510 reference manual *************/
/********************* CLKM3 ******************************************/
/* Traffic controller clock TC_CK is CK_GEN3/ARM_CKCTL.TCDIV. Idle mode is
controlled by ARM_IDLECT1.IDLIF_ARM. */
/* MPU interrupt handler uses TC_CK clock, which is set by
ARM_CKCTL.ARM_INTHCK_SEL. */
/* High speed bus clock HSAB_CK is equal to TC_CK. It is enabled by ARM_IDLECT2.ENHSAB_CK,
idle mode controlled by ARM_IDLECT1.IDLHSAB_ARM. */
/* Local bus and local bus MMU clock LB_CK is equal to TC_CK. It is enabled by
ARM_IDLECT2.EN_LBCK, idle mode controlled by ARM_IDLECT1.IDLLB_ARM.
NOTE. ARM_IDLECT2.EN_LBFREECK enables a separate clock LBFREE_CK, which can
continue to run while LB_CK is idled. */
/* MPU port interface clock API_CK is equal to TC_CK. It is enabled by ARM_IDLECT2.EN_APICK,
idle mode controlled by ARM_IDLECT1.IDLAPI_ARM. */
/* System DMA controller clock DMA_CK is equal to TC_CK. It is enabled by
ARM_IDLECT2.DMACK_REQ, idle mode controlled by ARM_IDLECT1.IDLIF_ARM. */
/* MPU peripheral bridge clocks, TIPB1a_CK, TIPB1b_CK, TIPB2a_CK and TIPB2b_ck are
equal to TC_CK. The idle mode is controlled by ARM_IDLECT1.IDLIF_ARM. */
/* LCD controller clock LCD_CK is CK_GEN3/ARM_CKCTL.LCDDIV. It is enabled by
ARM_IDLECT2.EN_LCKCK, idle mode controlled by ARM_IDLECT1.IDLLCD_ARM. */
/************ PAGE 840 and 841 of 1510 reference manual ******************/
struct MPU_CLK_reset_power_CTL_struct {
volatile unsigned short arm_ckctl;
volatile unsigned short reserved0;
volatile unsigned short arm_idlect1;
volatile unsigned short reserved1;
volatile unsigned short arm_idlect2;
volatile unsigned short reserved2;
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