fpga_peripherals.h

有关于USB的一些主机端驱动

/****************************************************************************
	 OMAP1510DC EVM Building project										
     Oct 3, 2001	China Digipro

	 File: FPGA_peripherals.h	     
     Content: Describes the FPGA peripheral interfaces
     Author: Zhu, Yaozong
*****************************************************************************/



/* FPGA on the 1510 evm board provides more control on peripherals.
   The ALTERA EPF10K100AFC484 FPGA device is attached to EMIFS.CS2 of 1510 device.
   This device synthesizes IO signals which are not implemented by 1510 itself. */
   

#if 1
struct FPGA_internal_register_set_struct {
	volatile unsigned char FPGA_versionlo; /* Readonly */
	volatile unsigned char FPGA_versionhi; /* Readonly */
	volatile unsigned char LCD_panel_CTL;
	volatile unsigned char digit_LED_CTL;
	volatile unsigned char HID_SPI;		  /* Partially readonly */
	volatile unsigned char power_CTL;
		#define SHDN_UART2_B 0x6 /* 0: Shutdown the Bluetooth UART driver MAX562; 1: Enable ................................... */
		#define SHDN_UART_B 0x5 /* 0: Shutdown the Giga UART driver MAX562; 1: Enable ..................................*/
		#define EN_48MHZ_CLK 0x2 /* Enable/Disable the external USB oscillator. */
		#define EN_4MHZ_CLK 0x1 /* Enable/Disable the HID and Touch Screen Controller oscillators. */
	volatile unsigned char INT_statuslo;
	volatile unsigned char INT_statushi;
	volatile unsigned char INT_masklo;
	volatile unsigned char INT_maskhi;
	volatile unsigned char host_reset;
	volatile unsigned char peripheral_reset;
	volatile unsigned char audio_CTL;
	volatile unsigned char reserved1;
	volatile unsigned char DIP_switch;	  /* Readonly */
	volatile unsigned char FPGA_IO;
	volatile unsigned char reserved2[0x08000013 - 0x08000010 + 1];
	volatile unsigned char UART1_EXT;	  /* Mostly readonly */
	volatile unsigned char UART2_EXT;	  /* Mostly readonly */
	volatile unsigned char EVM_status;	  /* Readonly */
	volatile unsigned char reserved3;
	volatile unsigned char board_revision; /* Readonly */
	volatile unsigned char reserved4;
	volatile unsigned char reserved5[0x080000FF - 0x0800001A + 1];      
	volatile unsigned char PPT_data;
	volatile unsigned char PPT_status;	  /* Readonly */
	volatile unsigned char PPT_CTL;
	volatile unsigned char reserved6[0x080001FF - 0x08000103 + 1];          
	
}; /* *pFPGA_IRS = (struct FPGA_internal_register_set_struct*)0x08000000; */
#endif


struct FPGA_ethernet_c196_register_set_struct {
	volatile unsigned short F0;
	volatile unsigned short F1;	
	volatile unsigned short F2;	
	volatile unsigned short F3;	
	volatile unsigned short F4;	
	volatile unsigned short F5;	
	volatile unsigned short F6;	
	volatile unsigned short F7;	
	volatile unsigned short F8;	
	volatile unsigned short F9;	
	volatile unsigned short FA;	
	volatile unsigned short FB;	
	volatile unsigned short FC;	
	volatile unsigned short FD;	
	volatile unsigned short FE;	
	volatile unsigned short FF;	
	
}; /*  *pFPGA_c196_IRS = (struct FPGA_ethernet_c196_register_set_struct*)0x08000300;*/