📄 omap30_tcif.h
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#define TC_EMIFS_CS2_CONFIG_FL_NUMB 1
#define TC_EMIFS_CS2_CONFIG_FL_RES_VAL 0x0
//R/W
#define TC_EMIFS_CS2_CONFIG_BW_POS 20
#define TC_EMIFS_CS2_CONFIG_BW_NUMB 1
#define TC_EMIFS_CS2_CONFIG_BW_RES_VAL 0x1
//R/W
#define TC_EMIFS_CS2_CONFIG_RDMODE_POS 16
#define TC_EMIFS_CS2_CONFIG_RDMODE_NUMB 3
#define TC_EMIFS_CS2_CONFIG_RDMODE_RES_VAL 0x0
//R/W
#define TC_EMIFS_CS2_CONFIG_PGWST_POS 12
#define TC_EMIFS_CS2_CONFIG_PGWST_NUMB 4
#define TC_EMIFS_CS2_CONFIG_PGWST_RES_VAL 0xF
//R/W
#define TC_EMIFS_CS2_CONFIG_WRWST_POS 8
#define TC_EMIFS_CS2_CONFIG_WRWST_NUMB 4
#define TC_EMIFS_CS2_CONFIG_WRWST_RES_VAL 0xF
//R/W
#define TC_EMIFS_CS2_CONFIG_RDWST_POS 4
#define TC_EMIFS_CS2_CONFIG_RDWST_NUMB 4
#define TC_EMIFS_CS2_CONFIG_RDWST_RES_VAL 0xF
//R/W
#define TC_EMIFS_CS2_CONFIG_RT_POS 2
#define TC_EMIFS_CS2_CONFIG_RT_NUMB 1
#define TC_EMIFS_CS2_CONFIG_RT_RES_VAL 0x0
//R/W
#define TC_EMIFS_CS2_CONFIG_FCLKDIV_POS 0
#define TC_EMIFS_CS2_CONFIG_FCLKDIV_NUMB 2
#define TC_EMIFS_CS2_CONFIG_FCLKDIV_RES_VAL 0x3
//R/W
//TC_EMIFS_CS3_CONFIG
//-------------------
#define TC_EMIFS_CS3_CONFIG REG32(TC_BASE_ADDR+0x1C)
#define TC_EMIFS_CS3_CONFIG_FL_POS 21
#define TC_EMIFS_CS3_CONFIG_FL_NUMB 1
#define TC_EMIFS_CS3_CONFIG_FL_RES_VAL 0x0
//R/W
#define TC_EMIFS_CS3_CONFIG_BW_POS 20
#define TC_EMIFS_CS3_CONFIG_BW_NUMB 1
#define TC_EMIFS_CS3_CONFIG_BW_RES_VAL 0x1
//R/W
#define TC_EMIFS_CS3_CONFIG_RDMODE_POS 16
#define TC_EMIFS_CS3_CONFIG_RDMODE_NUMB 3
#define TC_EMIFS_CS3_CONFIG_RDMODE_RES_VAL 0x0
//R/W
#define TC_EMIFS_CS3_CONFIG_PGWST_POS 12
#define TC_EMIFS_CS3_CONFIG_PGWST_NUMB 4
#define TC_EMIFS_CS3_CONFIG_PGWST_RES_VAL 0xF
//R/W
#define TC_EMIFS_CS3_CONFIG_WRWST_POS 8
#define TC_EMIFS_CS3_CONFIG_WRWST_NUMB 4
#define TC_EMIFS_CS3_CONFIG_WRWST_RES_VAL 0xF
//R/W
#define TC_EMIFS_CS3_CONFIG_RDWST_POS 4
#define TC_EMIFS_CS3_CONFIG_RDWST_NUMB 4
#define TC_EMIFS_CS3_CONFIG_RDWST_RES_VAL 0xF
//R/W
#define TC_EMIFS_CS3_CONFIG_RT_POS 2
#define TC_EMIFS_CS3_CONFIG_RT_NUMB 1
#define TC_EMIFS_CS3_CONFIG_RT_RES_VAL 0x0
//R/W
#define TC_EMIFS_CS3_CONFIG_FCLKDIV_POS 0
#define TC_EMIFS_CS3_CONFIG_FCLKDIV_NUMB 2
#define TC_EMIFS_CS3_CONFIG_FCLKDIV_RES_VAL 0x3
//R/W
//TC_EMIFF_SDRAM_CONFIG
//-------------------
#define TC_EMIFF_SDRAM_CONFIG REG32(TC_BASE_ADDR+0x20)
#define TC_EMIFF_SDRAM_CONFIG_CLK_POS 27
#define TC_EMIFF_SDRAM_CONFIG_CLK_NUMB 1
#define TC_EMIFF_SDRAM_CONFIG_CLK_RES_VAL 0x0
//R/W
#define TC_EMIFF_SDRAM_CONFIG_PWD_POS 26
#define TC_EMIFF_SDRAM_CONFIG_PWD_NUMB 1
#define TC_EMIFF_SDRAM_CONFIG_PWD_RES_VAL 0x0
//R/W
#define TC_EMIFF_SDRAM_CONFIG_SDRAMFREQ_POS 24
#define TC_EMIFF_SDRAM_CONFIG_SDRAMFREQ_NUMB 2
#define TC_EMIFF_SDRAM_CONFIG_SDRAMFREQ_RES_VAL 0x0
//R/W
#define TC_EMIFF_SDRAM_CONFIG_ARCV_POS 8
#define TC_EMIFF_SDRAM_CONFIG_ARCV_NUMB 16
#define TC_EMIFF_SDRAM_CONFIG_ARCV_RES_VAL 0x6188
//R/W
#define TC_EMIFF_SDRAM_CONFIG_SDRAMTYPE_POS 4
#define TC_EMIFF_SDRAM_CONFIG_SDRAMTYPE_NUMB 4
#define TC_EMIFF_SDRAM_CONFIG_SDRAMTYPE_RES_VAL 0x0
//R/W
#define TC_EMIFF_SDRAM_CONFIG_ARE_POS 2
#define TC_EMIFF_SDRAM_CONFIG_ARE_NUMB 2
#define TC_EMIFF_SDRAM_CONFIG_ARE_RES_VAL 0X0
//R/W
#define TC_EMIFF_SDRAM_CONFIG_SD_RET_POS 1
#define TC_EMIFF_SDRAM_CONFIG_SD_RET_NUMB 1
#define TC_EMIFF_SDRAM_CONFIG_SD_RET_RES_VAL 0x0
//R/W
#define TC_EMIFF_SDRAM_CONFIG_SLRF_POS 0
#define TC_EMIFF_SDRAM_CONFIG_SLRF_NUMB 1
#define TC_EMIFF_SDRAM_CONFIG_SLRF_RES_VAL 0x0
//R/W
//TC_EMIFF_MRS
//-------------------
#define TC_EMIFF_MRS REG32(TC_BASE_ADDR+0x24)
#define TC_EMIFF_MRS_WBST_POS 9
#define TC_EMIFF_MRS_WBST_NUMB 1
#define TC_EMIFF_MRS_WBST_RES_VAL 0x0
//R/W
#define TC_EMIFF_MRS_CASL_POS 4
#define TC_EMIFF_MRS_CASL_NUMB 3
#define TC_EMIFF_MRS_CASL_RES_VAL 0x3
//R/W
#define TC_EMIFF_MRS_SORI_POS 3
#define TC_EMIFF_MRS_SORI_NUMB 1
#define TC_EMIFF_MRS_SORI_RES_VAL 0x0
//R/W
#define TC_EMIFF_MRS_PGBL_POS 0
#define TC_EMIFF_MRS_PGBL_NUMB 3
#define TC_EMIFF_MRS_PGBL_RES_VAL 0x7
//R/W
//TC_TIMEOUT1
//-------------------
#define TC_TIMEOUT1 REG32(TC_BASE_ADDR+0x28)
#define TC_TIMEOUT1_LOCALBUS_POS 16
#define TC_TIMEOUT1_LOCALBUS_NUMB 8
#define TC_TIMEOUT1_LOCALBUS_RES_VAL 0x0
//R/W
#define TC_TIMEOUT1_DMA_POS 0
#define TC_TIMEOUT1_DMA_NUMB 8
#define TC_TIMEOUT1_DMA_RES_VAL 0x0
//R/W
//TC_TIMEOUT2
//-------------------
#define TC_TIMEOUT2 REG32(TC_BASE_ADDR+0x2C)
#define TC_TIMEOUT2_DSP_POS 16
#define TC_TIMEOUT2_DSP_NUMB 8
#define TC_TIMEOUT2_DSP_RES_VAL 0x0
//R/W
#define TC_TIMEOUT2_LCD_POS 0
#define TC_TIMEOUT2_LCD_NUMB 8
#define TC_TIMEOUT2_LCD_RES_VAL 0x0
//R/W
//TC_TIMEOUT3
//-------------------
#define TC_TIMEOUT3 REG32(TC_BASE_ADDR+0x30)
#define TC_TIMEOUT3_HSAB_POS 0
#define TC_TIMEOUT3_HSAB_NUMB 8
#define TC_TIMEOUT3_HSAB_RES_VAL 0x0
//R/W
//TC_ENDIANISM
//-------------------
#define TC_ENDIANISM REG32(TC_BASE_ADDR+0x34)
#define TC_ENDIANISM_SWAP_POS 1
#define TC_ENDIANISM_SWAP_NUMB 1
#define TC_ENDIANISM_SWAP_RES_VAL 0x0
//R/W
#define TC_ENDIANISM_EN_POS 0
#define TC_ENDIANISM_EN_NUMB 1
#define TC_ENDIANISM_EN_RES_VAL 0x0
//R/W
//-------------------------------------------------------------------------------
//
// GLOBAL DEFINITIONS
//
//-------------------------------------------------------------------------------
//EMIF Slow definition
#define TCIF_Slow_nCS0 0
#define TCIF_Slow_nCS1 1
#define TCIF_Slow_nCS2 2
#define TCIF_Slow_nCS3 3
#define BOOT_MODE_CS0 0
#define BOOT_MODE_CS3 1
#define FLASH_INTEL 1
#define NO_FLASH_INTEL 0
#define MEMORY_16BIT_WIDE 0
#define MEMORY_32BIT_WIDE 1
#define ASYNC_READ 0
#define PAGE_ROM_READ_WORDS4 1
#define PAGE_ROM_READ_WORDS8 2
#define PAGE_ROM_READ_WORDS16 3
#define SYNC_BURST_READ_TI 4
#define SYNC_BURST_READ_SMART3 5
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