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📄 omap30_tcif.h

📁 有关于USB的一些主机端驱动
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//-------------------------------------------------------------------------------
//          TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION  
//   Property of Texas Instruments
//   For Unrestricted Internal Use Only
//   Unauthorized reprofuction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work
//   Created 2000,  (C) Copyright 2000 Texas Instruments. All rights reserved
//
//-------------------------------------------------------------------------------
#ifndef _OMAP30_TCIF__H_
#define _OMAP30_TCIF__H_

//-------------------------------------------------------------------------------
//
//   ARM REGISTERS DECLARATION
//
//-------------------------------------------------------------------------------

#define            TC_BASE_ADDR                                                MEM_ARM_TC_ADDR

//TC_IMIF_PRIO
//-------------------
#define            TC_IMIF_PRIO                                                REG32(TC_BASE_ADDR+0x00)


#define            TC_IMIF_PRIO_HSAB_POS                                       16
#define            TC_IMIF_PRIO_HSAB_NUMB                                      3
#define            TC_IMIF_PRIO_HSAB_RES_VAL                                   0x0
//R/W

#define            TC_IMIF_PRIO_LBHOST_POS                                     12
#define            TC_IMIF_PRIO_LBHOST_NUMB                                    4
#define            TC_IMIF_PRIO_LBHOST_RES_VAL                                 0x0
//R/W

#define            TC_IMIF_PRIO_DMA_POS                                        8
#define            TC_IMIF_PRIO_DMA_NUMB                                       4
#define            TC_IMIF_PRIO_DMA_RES_VAL                                    0x0
//R/W

#define            TC_IMIF_PRIO_DSP_POS                                        4
#define            TC_IMIF_PRIO_DSP_NUMB                                       3
#define            TC_IMIF_PRIO_DSP_RES_VAL                                    0x0
//R/W

#define            TC_IMIF_PRIO_ARM_POS                                        0
#define            TC_IMIF_PRIO_ARM_NUMB                                       3
#define            TC_IMIF_PRIO_ARM_RES_VAL                                    0x0
//R/W


//TC_EMIFS_PRIO
//-------------------
#define            TC_EMIFS_PRIO                                               REG32(TC_BASE_ADDR+0x04)


#define            TC_EMIFS_PRIO_HSAB_POS                                      16
#define            TC_EMIFS_PRIO_HSAB_NUMB                                     3
#define            TC_EMIFS_PRIO_HSAB_RES_VAL                                  0x0
//R/W

#define            TC_EMIFS_PRIO_LBHOST_POS                                    12
#define            TC_EMIFS_PRIO_LBHOST_NUMB                                   4
#define            TC_EMIFS_PRIO_LBHOST_RES_VAL                                0x0
//R/W

#define            TC_EMIFS_PRIO_DMA_POS                                       8
#define            TC_EMIFS_PRIO_DMA_NUMB                                      4
#define            TC_EMIFS_PRIO_DMA_RES_VAL                                   0x0
//R/W

#define            TC_EMIFS_PRIO_DSP_POS                                       4
#define            TC_EMIFS_PRIO_DSP_NUMB                                      3
#define            TC_EMIFS_PRIO_DSP_RES_VAL                                   0x0
//R/W

#define            TC_EMIFS_PRIO_ARM_POS                                       0
#define            TC_EMIFS_PRIO_ARM_NUMB                                      3
#define            TC_EMIFS_PRIO_ARM_RES_VAL                                   0x0
//R/W


//TC_EMIFF_PRIO
//-------------------
#define            TC_EMIFF_PRIO                                               REG32(TC_BASE_ADDR+0x08)


#define            TC_EMIFF_PRIO_HSAB_POS                                      16
#define            TC_EMIFF_PRIO_HSAB_NUMB                                     3
#define            TC_EMIFF_PRIO_HSAB_RES_VAL                                  0x0
//R/W

#define            TC_EMIFF_PRIO_LBHOST_POS                                    12
#define            TC_EMIFF_PRIO_LBHOST_NUMB                                   4
#define            TC_EMIFF_PRIO_LBHOST_RES_VAL                                0x0
//R/W

#define            TC_EMIFF_PRIO_DMA_POS                                       8
#define            TC_EMIFF_PRIO_DMA_NUMB                                      4
#define            TC_EMIFF_PRIO_DMA_RES_VAL                                   0x0
//R/W

#define            TC_EMIFF_PRIO_DSP_POS                                       4
#define            TC_EMIFF_PRIO_DSP_NUMB                                      3
#define            TC_EMIFF_PRIO_DSP_RES_VAL                                   0x0
//R/W

#define            TC_EMIFF_PRIO_ARM_POS                                       0
#define            TC_EMIFF_PRIO_ARM_NUMB                                      3
#define            TC_EMIFF_PRIO_ARM_RES_VAL                                   0x0
//R/W


//TC_EMIFS_GLB_CONFIG
//-------------------
#define            TC_EMIFS_GLB_CONFIG                                         REG32(TC_BASE_ADDR+0x0C)


#define            TC_EMIFS_GLB_CONFIG_FR_POS                                  4
#define            TC_EMIFS_GLB_CONFIG_FR_NUMB                                 1
#define            TC_EMIFS_GLB_CONFIG_FR_RES_VAL                              0x0
//R

#define            TC_EMIFS_GLB_CONFIG_PDE_POS                                 3
#define            TC_EMIFS_GLB_CONFIG_PDE_NUMB                                1
#define            TC_EMIFS_GLB_CONFIG_PDE_RES_VAL                             0x0
//R/W

#define            TC_EMIFS_GLB_CONFIG_PWD_EN_POS                              2
#define            TC_EMIFS_GLB_CONFIG_PWD_EN_NUMB                             1
#define            TC_EMIFS_GLB_CONFIG_PWD_EN_RES_VAL                          0x0
//R/W

#define            TC_EMIFS_GLB_CONFIG_BM_POS                                  1
#define            TC_EMIFS_GLB_CONFIG_BM_NUMB                                 1
#define            TC_EMIFS_GLB_CONFIG_BM_RES_VAL                              0x0
//R

#define            TC_EMIFS_GLB_CONFIG_WP_POS                                  0
#define            TC_EMIFS_GLB_CONFIG_WP_NUMB                                 1
#define            TC_EMIFS_GLB_CONFIG_WP_RES_VAL                              0x0
//R/W


//TC_EMIFS_CS0_CONFIG
//-------------------
#define            TC_EMIFS_CS0_CONFIG                                         REG32(TC_BASE_ADDR+0x10)


#define            TC_EMIFS_CS0_CONFIG_FL_POS                                  21
#define            TC_EMIFS_CS0_CONFIG_FL_NUMB                                 1
#define            TC_EMIFS_CS0_CONFIG_FL_RES_VAL                              0x0
//R/W

#define            TC_EMIFS_CS0_CONFIG_BW_POS                                  20
#define            TC_EMIFS_CS0_CONFIG_BW_NUMB                                 1
#define            TC_EMIFS_CS0_CONFIG_BW_RES_VAL                              0x1
//R/W

#define            TC_EMIFS_CS0_CONFIG_RDMODE_POS                              16
#define            TC_EMIFS_CS0_CONFIG_RDMODE_NUMB                             3
#define            TC_EMIFS_CS0_CONFIG_RDMODE_RES_VAL                          0x0
//R/W

#define            TC_EMIFS_CS0_CONFIG_PGWST_POS                               12
#define            TC_EMIFS_CS0_CONFIG_PGWST_NUMB                              4
#define            TC_EMIFS_CS0_CONFIG_PGWST_RES_VAL                           0xF
//R/W

#define            TC_EMIFS_CS0_CONFIG_WRWST_POS                               8
#define            TC_EMIFS_CS0_CONFIG_WRWST_NUMB                              4
#define            TC_EMIFS_CS0_CONFIG_WRWST_RES_VAL                           0xF
//R/W

#define            TC_EMIFS_CS0_CONFIG_RDWST_POS                               4
#define            TC_EMIFS_CS0_CONFIG_RDWST_NUMB                              4
#define            TC_EMIFS_CS0_CONFIG_RDWST_RES_VAL                           0xF
//R/W

#define            TC_EMIFS_CS0_CONFIG_RT_POS                                  2
#define            TC_EMIFS_CS0_CONFIG_RT_NUMB                                 1
#define            TC_EMIFS_CS0_CONFIG_RT_RES_VAL                              0x0
//R/W

#define            TC_EMIFS_CS0_CONFIG_FCLKDIV_POS                             0
#define            TC_EMIFS_CS0_CONFIG_FCLKDIV_NUMB                            2
#define            TC_EMIFS_CS0_CONFIG_FCLKDIV_RES_VAL                         0x3
//R/W


//TC_EMIFS_CS1_CONFIG
//-------------------
#define            TC_EMIFS_CS1_CONFIG                                         REG32(TC_BASE_ADDR+0x14)


#define            TC_EMIFS_CS1_CONFIG_FL_POS                                  21
#define            TC_EMIFS_CS1_CONFIG_FL_NUMB                                 1
#define            TC_EMIFS_CS1_CONFIG_FL_RES_VAL                              0x0
//R/W

#define            TC_EMIFS_CS1_CONFIG_BW_POS                                  20
#define            TC_EMIFS_CS1_CONFIG_BW_NUMB                                 1
#define            TC_EMIFS_CS1_CONFIG_BW_RES_VAL                              0x1
//R/W

#define            TC_EMIFS_CS1_CONFIG_RDMODE_POS                              16
#define            TC_EMIFS_CS1_CONFIG_RDMODE_NUMB                             3
#define            TC_EMIFS_CS1_CONFIG_RDMODE_RES_VAL                          0x0
//R/W

#define            TC_EMIFS_CS1_CONFIG_PGWST_POS                               12
#define            TC_EMIFS_CS1_CONFIG_PGWST_NUMB                              4
#define            TC_EMIFS_CS1_CONFIG_PGWST_RES_VAL                           0xF
//R/W

#define            TC_EMIFS_CS1_CONFIG_WRWST_POS                               8
#define            TC_EMIFS_CS1_CONFIG_WRWST_NUMB                              4
#define            TC_EMIFS_CS1_CONFIG_WRWST_RES_VAL                           0xF
//R/W

#define            TC_EMIFS_CS1_CONFIG_RDWST_POS                               4
#define            TC_EMIFS_CS1_CONFIG_RDWST_NUMB                              4
#define            TC_EMIFS_CS1_CONFIG_RDWST_RES_VAL                           0xF
//R/W

#define            TC_EMIFS_CS1_CONFIG_RT_POS                                  2
#define            TC_EMIFS_CS1_CONFIG_RT_NUMB                                 1
#define            TC_EMIFS_CS1_CONFIG_RT_RES_VAL                              0x0
//R/W

#define            TC_EMIFS_CS1_CONFIG_FCLKDIV_POS                             0
#define            TC_EMIFS_CS1_CONFIG_FCLKDIV_NUMB                            2
#define            TC_EMIFS_CS1_CONFIG_FCLKDIV_RES_VAL                         0x3
//R/W


//TC_EMIFS_CS2_CONFIG
//-------------------
#define            TC_EMIFS_CS2_CONFIG                                         REG32(TC_BASE_ADDR+0x18)


#define            TC_EMIFS_CS2_CONFIG_FL_POS                                  21

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