omap30_armwdg.h

有关于USB的一些主机端驱动

//-------------------------------------------------------------------------------
//          TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION  
//   Property of Texas Instruments
//   For Unrestricted Internal Use Only
//   Unauthorized reprofuction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work
//   Created 2000,  (C) Copyright 2000 Texas Instruments. All rights reserved
//
//-------------------------------------------------------------------------------

#ifndef _OMAP30_ARMWDG__H_
#define _OMAP30_ARMWDG__H_

//-------------------------------------------------------------------------------
//
//   DSP REGISTERS DECLARATION
//
//-------------------------------------------------------------------------------

#define            ARMWDG_BASE_ADDR                                                MEM_ARM_WDG_TIMER_ADDR


//ARMWDG_CNTL_TIMER
//-------------------
#define            ARMWDG_CNTL_TIMER                                                               REG32(ARMWDG_BASE_ADDR+0x00)


#define            ARMWDG_CNTL_TIMER_PTV_POS                                                         9
#define            ARMWDG_CNTL_TIMER_PTV_NUMB                                                        3
#define            ARMWDG_CNTL_TIMER_PTV_RES_VAL                                                     0x0
//R/W

#define            ARMWDG_CNTL_TIMER_AR_POS                                                          8
#define            ARMWDG_CNTL_TIMER_AR_NUMB                                                         1
#define            ARMWDG_CNTL_TIMER_AR_RES_VAL                                                      0x0
//R/W

#define            ARMWDG_CNTL_TIMER_ST_POS                                                          7
#define            ARMWDG_CNTL_TIMER_ST_NUMB                                                         1
#define            ARMWDG_CNTL_TIMER_ST_RES_VAL                                                      0x0
//R/W

#define            ARMWDG_CNTL_TIMER_FREE_POS                                                        1
#define            ARMWDG_CNTL_TIMER_FREE_NUMB                                                       1
#define            ARMWDG_CNTL_TIMER_FREE_RES_VAL                                                    0x1
//R/W


//ARMWDG_READ_TIMER
//-------------------
#define            ARMWDG_READ_TIMER                                                               REG32(ARMWDG_BASE_ADDR+0x04)


#define            ARMWDG_READ_TIMER_LOAD_TIM_POS                                                    0
#define            ARMWDG_READ_TIMER_LOAD_TIM_NUMB                                                   16
#define            ARMWDG_READ_TIMER_LOAD_TIM_RES_VAL                                                0xFFFF
//W


//ARMWDG_LOAD_TIMER
//-------------------
#define            ARMWDG_LOAD_TIMER                                                               REG32(ARMWDG_BASE_ADDR+0x04)


#define            ARMWDG_LOAD_TIMER_VALUE_TIM_POS                                                   0
#define            ARMWDG_LOAD_TIMER_VALUE_TIM_NUMB                                                  16
#define            ARMWDG_LOAD_TIMER_VALUE_TIM_RES_VAL                                               0xFFFF
//R


//ARMWDG_TIMER_MODE
//-------------------
#define            ARMWDG_TIMER_MODE                                                               REG32(ARMWDG_BASE_ADDR+0x08)


#define            ARMWDG_TIMER_MODE_WATCHDOG_POS                                                    15
#define            ARMWDG_TIMER_MODE_WATCHDOG_NUMB                                                   1
#define            ARMWDG_TIMER_MODE_WATCHDOG_RES_VAL                                                0x1
//R/W

#define            ARMWDG_TIMER_MODE_WATCHDOG_DIS_POS                                                0
#define            ARMWDG_TIMER_MODE_WATCHDOG_DIS_NUMB                                               8
#define            ARMWDG_TIMER_MODE_WATCHDOG_DIS_RES_VAL                                            0x0
//W


//-------------------------------------------------------------------------------
//
//  FUNCTIONS
//
//-------------------------------------------------------------------------------

//----------------------------------------------------------
// NAME        : ARMWDG_Disable
// DESCRIPTION : Writting a predefined sequence
//               0xF5 followed by 0xA0 in the 8 lsb bits
//               to disable the watchdog
// PARAMETERS  : None
// RETURN VALUE: IS_OK if the watchdog has stopped 
//               NOT_OK if not
// ----------------------------------------------------------
UWORD16 ARMWDG_Disable(void);

//----------------------------------------------------------
// NAME        : ARMWDG_Enable
// DESCRIPTION : Set the wdg timer in Watchdog mode
//                                                     
// PARAMETERS  : None                                 
// RETURN VALUE: IS_OK if the watchdog run  
//               NOT_OK if not      
// ----------------------------------------------------------
UWORD16 ARMWDG_Enable(void);

//----------------------------------------------------------
// NAME        : ARMWDG_Refresh
// DESCRIPTION : Load a value in the watchdog to avoid a watchdog reset
//                                                     
// PARAMETERS  :
//   CounterValue = Timer setup value to be loaded                                 
// RETURN VALUE: None
// ----------------------------------------------------------
void ARMWDG_Refresh(UWORD16 CounterValue);


#endif  /* _OMAP30_ARMWDG__H_ */