omap30_sysdma.h

有关于USB的一些主机端驱动

//SYSDMA_DMA_CEI_CHX
//-------------------
#define            SYSDMA_DMA_CEI_CHX                                          REG16(SYSDMA_BASE_ADDR+SYSDMA_DMA_CEI_OFFSET)


#define            SYSDMA_DMA_CEI_CHX_CEI_POS                                    0
#define            SYSDMA_DMA_CEI_CHX_CEI_NUMB                                   16
#define            SYSDMA_DMA_CEI_CHX_CEI_RES_VAL                                0x0
//R/W


//SYSDMA_DMA_CPC_CHX
//-------------------
#define            SYSDMA_DMA_CPC_CHX                                          REG16(SYSDMA_BASE_ADDR+SYSDMA_DMA_CPC_OFFSET)


#define            SYSDMA_DMA_CPC_CHX_CPC_POS                                    0
#define            SYSDMA_DMA_CPC_CHX_CPC_NUMB                                   16
#define            SYSDMA_DMA_CPC_CHX_CPC_RES_VAL                                0x0
//R/W

     
//SYSDMA_DMA_LCD_CRTL
//-------------------
#define            SYSDMA_DMA_LCD_CRTL                                         REG16(SYSDMA_BASE_ADDR+SYSDMA_DMA_LCD_CRTL_OFFSET)

#define            DMA_LCD_SDRAM_SRC                                             0
#define            DMA_LCD_IMIF_SRC                                              1
#define            SYSDMA_DMA_LCD_CRTL_LCD_SOURCE_POS                            6
#define            SYSDMA_DMA_LCD_CRTL_LCD_SOURCE_NUMB                           1
#define            SYSDMA_DMA_LCD_CRTL_LCD_SOURCE_RES_VAL                        0x0
//R/W

#define            SYSDMA_DMA_LCD_CRTL_BUS_ERROR_IT_COND_POS                     5
#define            SYSDMA_DMA_LCD_CRTL_BUS_ERROR_IT_COND_NUMB                    1
#define            SYSDMA_DMA_LCD_CRTL_BUS_ERROR_IT_COND_RES_VAL                 0x0
//R

#define            SYSDMA_DMA_LCD_CRTL_FRAME_2_IT_COND_POS                       4
#define            SYSDMA_DMA_LCD_CRTL_FRAME_2_IT_COND_NUMB                      1
#define            SYSDMA_DMA_LCD_CRTL_FRAME_2_IT_COND_RES_VAL                   0x0
//R

#define            SYSDMA_DMA_LCD_CRTL_FRAME_1_IT_COND_POS                       3
#define            SYSDMA_DMA_LCD_CRTL_FRAME_1_IT_COND_NUMB                      1
#define            SYSDMA_DMA_LCD_CRTL_FRAME_1_IT_COND_RES_VAL                   0x0
//R

#define            SYSDMA_DMA_LCD_CRTL_BUS_ERROR_IT_IE_POS                       2
#define            SYSDMA_DMA_LCD_CRTL_BUS_ERROR_IT_IE_NUMB                      1
#define            SYSDMA_DMA_LCD_CRTL_BUS_ERROR_IT_IE_RES_VAL                   0x0
//R/W

#define            SYSDMA_DMA_LCD_CRTL_FRAME_IT_IE_POS                           1
#define            SYSDMA_DMA_LCD_CRTL_FRAME_IT_IE_NUMB                          1
#define            SYSDMA_DMA_LCD_CRTL_FRAME_IT_IE_RES_VAL                       0x0
//R/W

#define            SYSDMA_DMA_LCD_CRTL_FRAME_MODE_POS                            0
#define            SYSDMA_DMA_LCD_CRTL_FRAME_MODE_NUMB                           1
#define            SYSDMA_DMA_LCD_CRTL_FRAME_MODE_RES_VAL                        0x0
//R/W


//SYSDMA_DMA_LCD_TOP_F1_L
//-------------------
#define            SYSDMA_DMA_LCD_TOP_F1_L                                     REG16(SYSDMA_BASE_ADDR+SYSDMA_DMA_LCD_CRTL_OFFSET+SYSDMA_DMA_LCD_TOP_F1_L_OFFSET)


#define            SYSDMA_DMA_LCD_TOP_F1_L_ADD_L_POS                             0
#define            SYSDMA_DMA_LCD_TOP_F1_L_ADD_L_NUMB                            16
#define            SYSDMA_DMA_LCD_TOP_F1_L_ADD_L_RES_VAL                         0x0
//R/W

#define            SYSDMA_DMA_LCD_TOP_F1_L_ALWAYS0_POS                           0
#define            SYSDMA_DMA_LCD_TOP_F1_L_ALWAYS0_NUMB                          1
#define            SYSDMA_DMA_LCD_TOP_F1_L_ALWAYS0_RES_VAL                       0x0
//R/W


//SYSDMA_DMA_LCD_TOP_F1_U
//-------------------
#define            SYSDMA_DMA_LCD_TOP_F1_U                                     REG16(SYSDMA_BASE_ADDR+SYSDMA_DMA_LCD_CRTL_OFFSET+SYSDMA_DMA_LCD_TOP_F1_U_OFFSET)


#define            SYSDMA_DMA_LCD_TOP_F1_U_ADD_H_POS                             0
#define            SYSDMA_DMA_LCD_TOP_F1_U_ADD_H_NUMB                            16
#define            SYSDMA_DMA_LCD_TOP_F1_U_ADD_H_RES_VAL                         0x0
//R/W


//SYSDMA_DMA_LCD_BOT_F1_L
//-------------------
#define            SYSDMA_DMA_LCD_BOT_F1_L                                     REG16(SYSDMA_BASE_ADDR+SYSDMA_DMA_LCD_CRTL_OFFSET+SYSDMA_DMA_LCD_BOT_F1_L_OFFSET)


#define            SYSDMA_DMA_LCD_BOT_F1_L_ADD_L_POS                             0
#define            SYSDMA_DMA_LCD_BOT_F1_L_ADD_L_NUMB                            16
#define            SYSDMA_DMA_LCD_BOT_F1_L_ADD_L_RES_VAL                         0x0
//R/W

#define            SYSDMA_DMA_LCD_BOT_F1_L_ALWAYS0_POS                           0
#define            SYSDMA_DMA_LCD_BOT_F1_L_ALWAYS0_NUMB                          1
#define            SYSDMA_DMA_LCD_BOT_F1_L_ALWAYS0_RES_VAL                       0x0
//R


//SYSDMA_DMA_LCD_BOT_F1_U
//-------------------
#define            SYSDMA_DMA_LCD_BOT_F1_U                                     REG16(SYSDMA_BASE_ADDR+SYSDMA_DMA_LCD_CRTL_OFFSET+SYSDMA_DMA_LCD_BOT_F1_U_OFFSET)


#define            SYSDMA_DMA_LCD_BOT_F1_U_ADD_H_POS                             0
#define            SYSDMA_DMA_LCD_BOT_F1_U_ADD_H_NUMB                            16
#define            SYSDMA_DMA_LCD_BOT_F1_U_ADD_H_RES_VAL                         0x0
//R/W


//SYSDMA_DMA_LCD_TOP_F2_L
//-------------------
#define            SYSDMA_DMA_LCD_TOP_F2_L                                     REG16(SYSDMA_BASE_ADDR+SYSDMA_DMA_LCD_CRTL_OFFSET+SYSDMA_DMA_LCD_TOP_F2_L_OFFSET)


#define            SYSDMA_DMA_LCD_TOP_F2_L_ADD_L_POS                             0
#define            SYSDMA_DMA_LCD_TOP_F2_L_ADD_L_NUMB                            16
#define            SYSDMA_DMA_LCD_TOP_F2_L_ADD_L_RES_VAL                         0x0
//R/W

#define            SYSDMA_DMA_LCD_TOP_F2_L_ALWAYS0_POS                           0
#define            SYSDMA_DMA_LCD_TOP_F2_L_ALWAYS0_NUMB                          1
#define            SYSDMA_DMA_LCD_TOP_F2_L_ALWAYS0_RES_VAL                       0x0
//R


//SYSDMA_DMA_LCD_TOP_F2_U
//-------------------
#define            SYSDMA_DMA_LCD_TOP_F2_U                                     REG16(SYSDMA_BASE_ADDR+SYSDMA_DMA_LCD_CRTL_OFFSET+SYSDMA_DMA_LCD_TOP_F2_U_OFFSET)


#define            SYSDMA_DMA_LCD_TOP_F2_U_ADD_H_POS                             0
#define            SYSDMA_DMA_LCD_TOP_F2_U_ADD_H_NUMB                            16
#define            SYSDMA_DMA_LCD_TOP_F2_U_ADD_H_RES_VAL                         0x0
//R/W


//SYSDMA_DMA_LCD_BOT_F2_L
//-------------------
#define            SYSDMA_DMA_LCD_BOT_F2_L                                     REG16(SYSDMA_BASE_ADDR+SYSDMA_DMA_LCD_CRTL_OFFSET+SYSDMA_DMA_LCD_BOT_F2_L_OFFSET)


#define            SYSDMA_DMA_LCD_BOT_F2_L_ADD_L_POS                             0
#define            SYSDMA_DMA_LCD_BOT_F2_L_ADD_L_NUMB                            16
#define            SYSDMA_DMA_LCD_BOT_F2_L_ADD_L_RES_VAL                         0x0
//R/W

#define            SYSDMA_DMA_LCD_BOT_F2_L_ALWAYS0_POS                           0
#define            SYSDMA_DMA_LCD_BOT_F2_L_ALWAYS0_NUMB                          1
#define            SYSDMA_DMA_LCD_BOT_F2_L_ALWAYS0_RES_VAL                       0x0
//R


//SYSDMA_DMA_LCD_BOT_F2_U
//-------------------
#define            SYSDMA_DMA_LCD_BOT_F2_U                                     REG16(SYSDMA_BASE_ADDR+SYSDMA_DMA_LCD_CRTL_OFFSET+SYSDMA_DMA_LCD_BOT_F2_U_OFFSET)


#define            SYSDMA_DMA_LCD_BOT_F2_U_ADD_H_POS                             0
#define            SYSDMA_DMA_LCD_BOT_F2_U_ADD_H_NUMB                            16
#define            SYSDMA_DMA_LCD_BOT_F2_U_ADD_H_RES_VAL                         0x0
//R/W


//DMA_LCD_TOP_F1_L 
//---------------------------------------
#define     DMA_LCD_TOP_F1_L_POS          0
#define     DMA_LCD_TOP_F1_L_NUMB         16
#define     DMA_LCD_TOP_F1_L_MASK         0x0000FFFF

//DMA_LCD_TOP_F1_U 
//---------------------------------------
#define     DMA_LCD_TOP_F1_U_POS          0
#define     DMA_LCD_TOP_F1_U_NUMB         16
#define     DMA_LCD_TOP_F1_U_MASK         0xFFFF0000

#define     DMA_LCD_TOP_F1_RESET_VAL      0x0

//DMA_LCD_BOT_F1_L 
//---------------------------------------
#define     DMA_LCD_BOT_F1_L_POS          0
#define     DMA_LCD_BOT_F1_L_NUMB         16
#define     DMA_LCD_BOT_F1_L_MASK         0x0000FFFF

//DMA_LCD_BOT_F1_U 
//---------------------------------------
#define     DMA_LCD_BOT_F1_U_POS          0
#define     DMA_LCD_BOT_F1_U_NUMB         16
#define     DMA_LCD_BOT_F1_U_MASK         0xFFFF0000

#define     DMA_LCD_BOT_F1_RESET_VAL      0x0

//DMA_LCD_TOP_F2_L 
//---------------------------------------
#define     DMA_LCD_TOP_F2_L_POS          0
#define     DMA_LCD_TOP_F2_L_NUMB         16
#define     DMA_LCD_TOP_F2_L_MASK         0x0000FFFF

//DMA_LCD_TOP_F2_U 
//---------------------------------------
#define     DMA_LCD_TOP_F2_U_POS          0
#define     DMA_LCD_TOP_F2_U_NUMB         16
#define     DMA_LCD_TOP_F2_U_MASK         0xFFFF0000

#define     DMA_LCD_TOP_F2_RESET_VAL      0x0

//DMA_LCD_BOT_F2_L 
//---------------------------------------
#define     DMA_LCD_BOT_F2_L_POS          0
#define     DMA_LCD_BOT_F2_L_NUMB         16
#define     DMA_LCD_BOT_F2_L_MASK         0x0000FFFF

//DMA_LCD_BOT_F2_U 
//---------------------------------------
#define     DMA_LCD_BOT_F2_U_POS          0
#define     DMA_LCD_BOT_F2_U_NUMB         16
#define     DMA_LCD_BOT_F2_U_MASK         0xFFFF0000

#define     DMA_LCD_BOT_F2_RESET_VAL      0x0

//-------------------------------------------------------------------------------
//
//   GLOBAL TYPES DEFINITION
//
//-------------------------------------------------------------------------------

// Total Number of channels 
#define DMA_NUMBER_OF_CHANNEL  9

// ChannelNumb
#define     DMA_CHANNEL_0    0
#define     DMA_CHANNEL_1    1
#define     DMA_CHANNEL_2    2
#define     DMA_CHANNEL_3    3
#define     DMA_CHANNEL_4    4
#define     DMA_CHANNEL_5    5
#define     DMA_CHANNEL_6    6
#define     DMA_CHANNEL_7    7
#define     DMA_CHANNEL_8    8
#define     DMA_CHANNEL_LCD  12

//   Channel DMA global register structure
typedef struct
{

  BIT    Free:1;
  BIT    AutogatingOn:1;

}
GLOBAL_REGISTER ;

//   Channel DMA descriptor structure
typedef struct
{

  BIT    ChannelNumb:4;

   //DMA_CSDP
   //--------------------
  BIT    TypeSize:2;

  BIT    SrcPort:3;
  BIT    DestPort:3;

  BIT    SrcPack:1;
  BIT    DestPack:1;

  BIT    SrcBurst:2;
  BIT    DestBurst:2;

   //DMA_CCR
   //-----------------------
  BIT    SyncNumb:5;
  BIT    SyncPr:1;
  BIT    EventSync:1;//fs
  BIT    Priority:1;
  BIT    Enable:1;
  BIT    Autoinit:1;
  BIT    Fifofush:1;

  BIT    SrcAddressMode:2;
  BIT    DestAddressMode:2;

    //DMA_CICR
    //----------------------
  BIT    TimeoutIntEnable:1;
  BIT    DropIntEnable:1;
  BIT    HalfFrameIntEnable:1;
  BIT    FrameIntEnable:1;
  BIT    LastFrameIntEnable:1;
  BIT    BlockIntEnable:1;

    //DMA_CSCR
    //----------------------
  BIT    TimeoutInt:1;
  BIT    DropInt:1;
  BIT    HalfFrameInt:1;
  BIT    FrameInt:1;
  BIT    LastFrameInt:1;
  BIT    BlockInt:1;

    //DMA_CSSA L and U
    //----------------------
  UWORD32    SrcAdd;

    //DMA_CDSA L and U