📄 omap30_sysdma.h
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//-------------------------------------------------------------------------------
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reprofuction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work
// Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved
//
//-------------------------------------------------------------------------------
#ifndef _OMAP30_SYSDMA__H_
#define _OMAP30_SYSDMA__H_
//-------------------------------------------------------------------------------
//
// ARM REGISTERS DECLARATION
//
//-------------------------------------------------------------------------------
#define SYSDMA_BASE_ADDR MEM_ARM_DMA_CONTROLLER_ADDR
#define SYSDMA_DMA_GCR_OFFSET 0x400
#define SYSDMA_DMA_CSDP_OFFSET 0x00
#define SYSDMA_DMA_CCR_OFFSET 0x02
#define SYSDMA_DMA_CICR_OFFSET 0x04
#define SYSDMA_DMA_CSR_OFFSET 0x06
#define SYSDMA_DMA_CSSA_L_OFFSET 0x08
#define SYSDMA_DMA_CSSA_U_OFFSET 0x0A
#define SYSDMA_DMA_CDSA_L_OFFSET 0x0C
#define SYSDMA_DMA_CDSA_U_OFFSET 0x0E
#define SYSDMA_DMA_CEN_OFFSET 0x10
#define SYSDMA_DMA_CFN_OFFSET 0x12
#define SYSDMA_DMA_CFI_OFFSET 0x14
#define SYSDMA_DMA_CEI_OFFSET 0x16
#define SYSDMA_DMA_CPC_OFFSET 0x18
#define SYSDMA_DMA_LCD_CRTL_OFFSET 0x300
#define SYSDMA_DMA_LCD_TOP_F1_L_OFFSET 0x02
#define SYSDMA_DMA_LCD_TOP_F1_U_OFFSET 0x04
#define SYSDMA_DMA_LCD_BOT_F1_L_OFFSET 0x06
#define SYSDMA_DMA_LCD_BOT_F1_U_OFFSET 0x08
#define SYSDMA_DMA_LCD_TOP_F2_L_OFFSET 0x0A
#define SYSDMA_DMA_LCD_TOP_F2_U_OFFSET 0x0C
#define SYSDMA_DMA_LCD_BOT_F2_L_OFFSET 0x0E
#define SYSDMA_DMA_LCD_BOT_F2_U_OFFSET 0x10
//SYSDMA_DMA_GCR
//-------------------
#define SYSDMA_DMA_GCR REG16(SYSDMA_BASE_ADDR+SYSDMA_DMA_GCR_OFFSET)
#define SYSDMA_DMA_GCR_ADD (SYSDMA_BASE_ADDR+SYSDMA_DMA_GCR_OFFSET)
#define SYSDMA_DMA_GCR_AUTOGATING_ON_POS 3
#define SYSDMA_DMA_GCR_AUTOGATING_ON_NUMB 1
#define SYSDMA_DMA_GCR_AUTOGATING_ON_RES_VAL 0x1
//R/W
#define SYSDMA_DMA_GCR_FREE_POS 2
#define SYSDMA_DMA_GCR_FREE_NUMB 1
#define SYSDMA_DMA_GCR_FREE_RES_VAL 0x0
//R/W
//SYSDMA_DMA_CSDP_CHX
//-------------------
#define SYSDMA_DMA_CSDP_CHX REG16(SYSDMA_BASE_ADDR+SYSDMA_DMA_CSDP_OFFSET)
#define SYSDMA_DMA_CSDP_CHX_DST_BURST_EN_POS 14
#define SYSDMA_DMA_CSDP_CHX_DST_BURST_EN_NUMB 2
#define SYSDMA_DMA_CSDP_CHX_DST_BURST_EN_RES_VAL 0x00
//R/W
#define SYSDMA_DMA_CSDP_CHX_DST_PACK_POS 13
#define SYSDMA_DMA_CSDP_CHX_DST_PACK_NUMB 1
#define SYSDMA_DMA_CSDP_CHX_DST_PACK_RES_VAL 0x0
//R/W
#define SYSDMA_DMA_CSDP_CHX_DST_POS 9
#define SYSDMA_DMA_CSDP_CHX_DST_NUMB 4
#define SYSDMA_DMA_CSDP_CHX_DST_RES_VAL 0x0000
//R/W
#define SYSDMA_DMA_CSDP_CHX_SRC_BURST_EN_POS 7
#define SYSDMA_DMA_CSDP_CHX_SRC_BURST_EN_NUMB 2
#define SYSDMA_DMA_CSDP_CHX_SRC_BURST_EN_RES_VAL 0x00
//R/W
#define SYSDMA_DMA_CSDP_CHX_SRC_PACK_POS 6
#define SYSDMA_DMA_CSDP_CHX_SRC_PACK_NUMB 1
#define SYSDMA_DMA_CSDP_CHX_SRC_PACK_RES_VAL 0x0
//R/W
#define SYSDMA_DMA_CSDP_CHX_SRC_POS 2
#define SYSDMA_DMA_CSDP_CHX_SRC_NUMB 4
#define SYSDMA_DMA_CSDP_CHX_SRC_RES_VAL 0x0000
//R/W
#define SYSDMA_DMA_CSDP_CHX_DATA_TYPE_POS 0
#define SYSDMA_DMA_CSDP_CHX_DATA_TYPE_NUMB 2
#define SYSDMA_DMA_CSDP_CHX_DATA_TYPE_RES_VAL 0x00
//R/W
//SYSDMA_DMA_CCR_CHX
//-------------------
#define SYSDMA_DMA_CCR_CHX REG16(SYSDMA_BASE_ADDR+SYSDMA_DMA_CCR_OFFSET)
#define SYSDMA_DMA_CCR_CHX_DST_AMODE_POS 14
#define SYSDMA_DMA_CCR_CHX_DST_AMODE_NUMB 2
#define SYSDMA_DMA_CCR_CHX_DST_AMODE_RES_VAL 0x00
//R/W
#define SYSDMA_DMA_CCR_CHX_SRC_AMODE_POS 12
#define SYSDMA_DMA_CCR_CHX_SRC_AMODE_NUMB 2
#define SYSDMA_DMA_CCR_CHX_SRC_AMODE_RES_VAL 0x00
//R/W
#define SYSDMA_DMA_CCR_CHX_END_PROG_POS 11
#define SYSDMA_DMA_CCR_CHX_END_PROG_NUMB 1
#define SYSDMA_DMA_CCR_CHX_END_PROG_RES_VAL 0x0
//R/W
#define SYSDMA_DMA_CCR_CHX_FIFO_FLUSH_POS 10
#define SYSDMA_DMA_CCR_CHX_FIFO_FLUSH_NUMB 1
#define SYSDMA_DMA_CCR_CHX_FIFO_FLUSH_RES_VAL 0x0
//R/W
#define SYSDMA_DMA_CCR_CHX_REPEAT_POS 9
#define SYSDMA_DMA_CCR_CHX_REPEAT_NUMB 1
#define SYSDMA_DMA_CCR_CHX_REPEAT_RES_VAL 0x0
//R/W
#define SYSDMA_DMA_CCR_CHX_AUTO_INIT_POS 8
#define SYSDMA_DMA_CCR_CHX_AUTO_INIT_NUMB 1
#define SYSDMA_DMA_CCR_CHX_AUTO_INIT_RES_VAL 0x0
//R/W
#define SYSDMA_DMA_CCR_CHX_EN_POS 7
#define SYSDMA_DMA_CCR_CHX_EN_NUMB 1
#define SYSDMA_DMA_CCR_CHX_EN_RES_VAL 0x0
//R/W
#define SYSDMA_DMA_CCR_CHX_PRIO_POS 6
#define SYSDMA_DMA_CCR_CHX_PRIO_NUMB 1
#define SYSDMA_DMA_CCR_CHX_PRIO_RES_VAL 0x0
//R/W
#define SYSDMA_DMA_CCR_CHX_FS_POS 5
#define SYSDMA_DMA_CCR_CHX_FS_NUMB 1
#define SYSDMA_DMA_CCR_CHX_FS_RES_VAL 0x0
//R/W
#define SYSDMA_DMA_CCR_CHX_SYNC_PR_POS 4
#define SYSDMA_DMA_CCR_CHX_SYNC_PR_NUMB 1
#define SYSDMA_DMA_CCR_CHX_SYNC_PR_RES_VAL 0x0
//R/W
#define SYSDMA_DMA_CCR_CHX_SYNC_POS 0
#define SYSDMA_DMA_CCR_CHX_SYNC_NUMB 4
#define SYSDMA_DMA_CCR_CHX_SYNC_RES_VAL 0x0000
//R/W
//SYSDMA_DMA_CICR_CHX
//-------------------
#define SYSDMA_DMA_CICR_CHX REG16(SYSDMA_BASE_ADDR+SYSDMA_DMA_CICR_OFFSET)
#define SYSDMA_DMA_CICR_CHX_BLOCK_IE_POS 5
#define SYSDMA_DMA_CICR_CHX_BLOCK_IE_NUMB 1
#define SYSDMA_DMA_CICR_CHX_BLOCK_IE_RES_VAL 0x0
//R/W
#define SYSDMA_DMA_CICR_CHX_LAST_IE_POS 4
#define SYSDMA_DMA_CICR_CHX_LAST_IE_NUMB 1
#define SYSDMA_DMA_CICR_CHX_LAST_IE_RES_VAL 0x0
//R/W
#define SYSDMA_DMA_CICR_CHX_FRAME_IE_POS 3
#define SYSDMA_DMA_CICR_CHX_FRAME_IE_NUMB 1
#define SYSDMA_DMA_CICR_CHX_FRAME_IE_RES_VAL 0x0
//R/W
#define SYSDMA_DMA_CICR_CHX_HALF_IE_POS 2
#define SYSDMA_DMA_CICR_CHX_HALF_IE_NUMB 1
#define SYSDMA_DMA_CICR_CHX_HALF_IE_RES_VAL 0x0
//R/W
#define SYSDMA_DMA_CICR_CHX_DROP_IE_POS 1
#define SYSDMA_DMA_CICR_CHX_DROP_IE_NUMB 1
#define SYSDMA_DMA_CICR_CHX_DROP_IE_RES_VAL 0x1
//R/W
#define SYSDMA_DMA_CICR_CHX_TOUT_IE_POS 0
#define SYSDMA_DMA_CICR_CHX_TOUT_IE_NUMB 1
#define SYSDMA_DMA_CICR_CHX_TOUT_IE_RES_VAL 0x1
//R/W
//SYSDMA_DMA_CSR_CHX
//-------------------
#define SYSDMA_DMA_CSR_CHX REG16(SYSDMA_BASE_ADDR+SYSDMA_DMA_CSR_OFFSET)
#define SYSDMA_DMA_CSR_CHX_SYNC_POS 6
#define SYSDMA_DMA_CSR_CHX_SYNC_NUMB 1
#define SYSDMA_DMA_CSR_CHX_SYNC_RES_VAL 0x0
//R/W
#define SYSDMA_DMA_CSR_CHX_BLOCK_POS 5
#define SYSDMA_DMA_CSR_CHX_BLOCK_NUMB 1
#define SYSDMA_DMA_CSR_CHX_BLOCK_RES_VAL 0x0
//R/W
#define SYSDMA_DMA_CSR_CHX_LAST_POS 4
#define SYSDMA_DMA_CSR_CHX_LAST_NUMB 1
#define SYSDMA_DMA_CSR_CHX_LAST_RES_VAL 0x0
//R/W
#define SYSDMA_DMA_CSR_CHX_FRAME_POS 3
#define SYSDMA_DMA_CSR_CHX_FRAME_NUMB 1
#define SYSDMA_DMA_CSR_CHX_FRAME_RES_VAL 0x0
//R/W
#define SYSDMA_DMA_CSR_CHX_HALF_POS 2
#define SYSDMA_DMA_CSR_CHX_HALF_NUMB 1
#define SYSDMA_DMA_CSR_CHX_HALF_RES_VAL 0x0
//R/W
#define SYSDMA_DMA_CSR_CHX_DROP_POS 1
#define SYSDMA_DMA_CSR_CHX_DROP_NUMB 1
#define SYSDMA_DMA_CSR_CHX_DROP_RES_VAL 0x0
//R/W
#define SYSDMA_DMA_CSR_CHX_TOUT_POS 0
#define SYSDMA_DMA_CSR_CHX_TOUT_NUMB 1
#define SYSDMA_DMA_CSR_CHX_TOUT_RES_VAL 0x0
//R/W
//SYSDMA_DMA_CSSA_L_CHX
//-------------------
#define SYSDMA_DMA_CSSA_L_CHX REG16(SYSDMA_BASE_ADDR+SYSDMA_DMA_CSSA_L_OFFSET)
#define SYSDMA_DMA_CSSA_L_CHX_CSSA_L_POS 0
#define SYSDMA_DMA_CSSA_L_CHX_CSSA_L_NUMB 16
#define SYSDMA_DMA_CSSA_L_CHX_CSSA_L_RES_VAL 0x0
//R/W
//SYSDMA_DMA_CSSA_U_CHX
//-------------------
#define SYSDMA_DMA_CSSA_U_CHX REG16(SYSDMA_BASE_ADDR+SYSDMA_DMA_CSSA_U_OFFSET)
#define SYSDMA_DMA_CSSA_U_CHX_CSSA_U_POS 0
#define SYSDMA_DMA_CSSA_U_CHX_CSSA_U_NUMB 16
#define SYSDMA_DMA_CSSA_U_CHX_CSSA_U_RES_VAL 0x0
//R/W
//SYSDMA_DMA_CDSA_L_CHX
//-------------------
#define SYSDMA_DMA_CDSA_L_CHX REG16(SYSDMA_BASE_ADDR+SYSDMA_DMA_CDSA_L_OFFSET)
#define SYSDMA_DMA_CDSA_L_CHX_CDSA_L_POS 0
#define SYSDMA_DMA_CDSA_L_CHX_CDSA_L_NUMB 16
#define SYSDMA_DMA_CDSA_L_CHX_CDSA_L_RES_VAL 0x0
//R/W
//SYSDMA_DMA_CDSA_U_CHX
//-------------------
#define SYSDMA_DMA_CDSA_U_CHX REG16(SYSDMA_BASE_ADDR+SYSDMA_DMA_CDSA_U_OFFSET)
#define SYSDMA_DMA_CDSA_U_CHX_CDSA_U_POS 0
#define SYSDMA_DMA_CDSA_U_CHX_CDSA_U_NUMB 16
#define SYSDMA_DMA_CDSA_U_CHX_CDSA_U_RES_VAL 0x0
//R/W
//SYSDMA_DMA_CEN_CHX
//-------------------
#define SYSDMA_DMA_CEN_CHX REG16(SYSDMA_BASE_ADDR+SYSDMA_DMA_CEN_OFFSET)
#define SYSDMA_DMA_CEN_CHX_CEN_POS 0
#define SYSDMA_DMA_CEN_CHX_CEN_NUMB 16
#define SYSDMA_DMA_CEN_CHX_CEN_RES_VAL 0x0
//R/W
//SYSDMA_DMA_CFN_CHX
//-------------------
#define SYSDMA_DMA_CFN_CHX REG16(SYSDMA_BASE_ADDR+SYSDMA_DMA_CFN_OFFSET)
#define SYSDMA_DMA_CFN_CHX_CFN_POS 0
#define SYSDMA_DMA_CFN_CHX_CFN_NUMB 16
#define SYSDMA_DMA_CFN_CHX_CFN_RES_VAL 0x0
//R/W
//SYSDMA_DMA_CFI_CHX
//-------------------
#define SYSDMA_DMA_CFI_CHX REG16(SYSDMA_BASE_ADDR+SYSDMA_DMA_CFI_OFFSET)
#define SYSDMA_DMA_CFI_CHX_CFI_POS 0
#define SYSDMA_DMA_CFI_CHX_CFI_NUMB 16
#define SYSDMA_DMA_CFI_CHX_CFI_RES_VAL 0x0
//R/W
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