📄 omap30_mmu.h
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//R/W
//HSABMMU_CAM_H_REG
//-------------------
#define HSABMMU_CAM_H_REG REG32(MEM_ARM_HSAB_MMU_ADDR+0x2C)
#define HSABMMU_CAM_H_REG_VA_TAG_LL_H_POS 0
#define HSABMMU_CAM_H_REG_VA_TAG_LL_H_NUMB 16
#define HSABMMU_CAM_H_REG_VA_TAG_LL_H_RES_VAL 0x0
//R/W
//HSABMMU_CAM_L_REG
//-------------------
#define HSABMMU_CAM_L_REG REG32(MEM_ARM_HSAB_MMU_ADDR+0x30)
#define HSABMMU_CAM_L_REG_VA_TAGL1_L_POS 14
#define HSABMMU_CAM_L_REG_VA_TAGL1_L_NUMB 2
#define HSABMMU_CAM_L_REG_VA_TAGL1_L_RES_VAL 0x0
//R/W
#define HSABMMU_CAM_L_REG_VA_TAG_I2_POS 4
#define HSABMMU_CAM_L_REG_VA_TAG_I2_NUMB 10
#define HSABMMU_CAM_L_REG_VA_TAG_I2_RES_VAL 0x0
//R/W
#define HSABMMU_CAM_L_REG_P_POS 3
#define HSABMMU_CAM_L_REG_P_NUMB 1
#define HSABMMU_CAM_L_REG_P_RES_VAL 0x0
//R/W
#define HSABMMU_CAM_L_REG_V_POS 2
#define HSABMMU_CAM_L_REG_V_NUMB 1
#define HSABMMU_CAM_L_REG_V_RES_VAL 0x0
//R
#define HSABMMU_CAM_L_REG_SLTS_POS 0
#define HSABMMU_CAM_L_REG_SLTS_NUMB 2
#define HSABMMU_CAM_L_REG_SLTS_RES_VAL 0x0
//R/W
//HSABMMU_RAM_H_REG
//-------------------
#define HSABMMU_RAM_H_REG REG32(MEM_ARM_HSAB_MMU_ADDR+0x34)
#define HSABMMU_RAM_H_REG_RAM_MSB_POS 0
#define HSABMMU_RAM_H_REG_RAM_MSB_NUMB 16
#define HSABMMU_RAM_H_REG_RAM_MSB_RES_VAL 0x0
//R/W
//HSABMMU_RAM_L_REG
//-------------------
#define HSABMMU_RAM_L_REG REG32(MEM_ARM_HSAB_MMU_ADDR+0x38)
#define HSABMMU_RAM_L_REG_RAM_LSB_POS 10
#define HSABMMU_RAM_L_REG_RAM_LSB_NUMB 6
#define HSABMMU_RAM_L_REG_RAM_LSB_RES_VAL 0x0
//R/W
#define HSABMMU_RAM_L_REG_AP_POS 8
#define HSABMMU_RAM_L_REG_AP_NUMB 2
#define HSABMMU_RAM_L_REG_AP_RES_VAL 0x0
//R/W
//HSABMMU_GFLUSH_REG
//-------------------
#define HSABMMU_GFLUSH_REG REG32(MEM_ARM_HSAB_MMU_ADDR+0x3C)
#define HSABMMU_GFLUSH_REG_GLOBAL_FLUSH_POS 0
#define HSABMMU_GFLUSH_REG_GLOBAL_FLUSH_NUMB 1
#define HSABMMU_GFLUSH_REG_GLOBAL_FLUSH_RES_VAL 0x0
//R/W
//HSABMMU_FLUSH_ENTRY_REG
//-------------------
#define HSABMMU_FLUSH_ENTRY_REG REG32(MEM_ARM_HSAB_MMU_ADDR+0x40)
#define HSABMMU_FLUSH_ENTRY_REG_FLUSH_ENTRY_POS 0
#define HSABMMU_FLUSH_ENTRY_REG_FLUSH_ENTRY_NUMB 1
#define HSABMMU_FLUSH_ENTRY_REG_FLUSH_ENTRY_RES_VAL 0x0
//R/W
//HSABMMU_READ_CAM_H_REG
//-------------------
#define HSABMMU_READ_CAM_H_REG REG32(MEM_ARM_HSAB_MMU_ADDR+0x44)
#define HSABMMU_READ_CAM_H_REG_READ_CAM_H_POS 0
#define HSABMMU_READ_CAM_H_REG_READ_CAM_H_NUMB 16
#define HSABMMU_READ_CAM_H_REG_READ_CAM_H_RES_VAL 0x0
//R/W
//HSABMMU_READ_CAM_L_REG
//-------------------
#define HSABMMU_READ_CAM_L_REG REG32(MEM_ARM_HSAB_MMU_ADDR+0x48)
#define HSABMMU_READ_CAM_L_REG_VA_TAG_I2_POS 4
#define HSABMMU_READ_CAM_L_REG_VA_TAG_I2_NUMB 10
#define HSABMMU_READ_CAM_L_REG_VA_TAG_I2_RES_VAL 0x0
//R/W
#define HSABMMU_READ_CAM_L_REG_P_POS 3
#define HSABMMU_READ_CAM_L_REG_P_NUMB 1
#define HSABMMU_READ_CAM_L_REG_P_RES_VAL 0x0
//R/W
#define HSABMMU_READ_CAM_L_REG_V_POS 2
#define HSABMMU_READ_CAM_L_REG_V_NUMB 1
#define HSABMMU_READ_CAM_L_REG_V_RES_VAL 0x0
//R
#define HSABMMU_READ_CAM_L_REG_SLTS_POS 0
#define HSABMMU_READ_CAM_L_REG_SLTS_NUMB 2
#define HSABMMU_READ_CAM_L_REG_SLTS_RES_VAL 0x0
//R/W
//HSABMMU_READ_RAM_H_REG
//-------------------
#define HSABMMU_READ_RAM_H_REG REG32(MEM_ARM_HSAB_MMU_ADDR+0x4C)
#define HSABMMU_READ_RAM_H_REG_READ_RAM_H_POS 0
#define HSABMMU_READ_RAM_H_REG_READ_RAM_H_NUMB 16
#define HSABMMU_READ_RAM_H_REG_READ_RAM_H_RES_VAL 0x0
//R/W
//HSABMMU_READ_RAM_L_REG
//-------------------
#define HSABMMU_READ_RAM_L_REG REG32(MEM_ARM_HSAB_MMU_ADDR+0x50)
#define HSABMMU_READ_RAM_L_REG_RAM_LSB_POS 10
#define HSABMMU_READ_RAM_L_REG_RAM_LSB_NUMB 6
#define HSABMMU_READ_RAM_L_REG_RAM_LSB_RES_VAL 0x0
//R/W
#define HSABMMU_READ_RAM_L_REG_AP_POS 7
#define HSABMMU_READ_RAM_L_REG_AP_NUMB 3
#define HSABMMU_READ_RAM_L_REG_AP_RES_VAL 0x0
//R/W
//-------------------------------------------------------------------------------
//
// GLOBAL TYPES DEFINITION
//
//-------------------------------------------------------------------------------
typedef enum { DSP_MMU, LB_MMU, HSAB_MMU } MMU_NAME_t;
typedef enum { TRANS_FAULT = 1, TLB_MISS = 2,
PERM_FAULT = 4, PREFETCH_ERR = 8 } FAULT_STATUS_t;
typedef enum { SECTION = 0, LARGE_PAGE = 1,
SMALL_PAGE = 2, TINY_PAGE = 3 } SLST_t;
typedef enum { ENTRY_NOT_PRESERVED = 0, ENTRY_PRESERVED = 1 } PRESERVED_t;
typedef enum { NOT_ACCESSIBLE = 0, READ_ONLY = 2, FULL_ACCESS = 3 } AP_t;
//-------------------------------------------------------------------------------
//
// FUNCTIONS
//
//-------------------------------------------------------------------------------
//-------------------------------------------------------------------------------
// NAME : MMU_Reset
// DESCRIPTION : Resets the module. The module comes back to default config
// PARAMETERS : mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU
// RETURN VALUE: None.
// LIMITATIONS : None.
//-------------------------------------------------------------------------------
void MMU_Reset(MMU_NAME_t mmu_name);
//-------------------------------------------------------------------------------
// NAME : MMU_Release_Reset
// DESCRIPTION : Release Reset of module.
// PARAMETERS : mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU
// RETURN VALUE: None.
// LIMITATIONS : None.
//-------------------------------------------------------------------------------
void MMU_Release_Reset(MMU_NAME_t mmu_name);
//-------------------------------------------------------------------------------
// NAME : MMU_Enable
// DESCRIPTION : Enables MMU
// PARAMETERS : mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU
// RETURN VALUE: None.
// LIMITATIONS : None.
//-------------------------------------------------------------------------------
void MMU_Enable(MMU_NAME_t mmu_name);
//-------------------------------------------------------------------------------
// NAME : MMU_Disable
// DESCRIPTION : Disables MMU
// PARAMETERS : mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU
// RETURN VALUE: None.
// LIMITATIONS : None.
//-------------------------------------------------------------------------------
void MMU_Disable(MMU_NAME_t mmu_name);
//-------------------------------------------------------------------------------
// NAME : MMU_Enable_WTL
// DESCRIPTION : Enables Walking Table Logic
// PARAMETERS : mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU
// RETURN VALUE: None.
// LIMITATIONS : None.
//-------------------------------------------------------------------------------
void MMU_Enable_WTL(MMU_NAME_t mmu_name);
//-------------------------------------------------------------------------------
// NAME : MMU_Disable_WTL
// DESCRIPTION : Disables Walking Table Logic
// PARAMETERS : mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU
// RETURN VALUE: None.
// LIMITATIONS : None.
//-------------------------------------------------------------------------------
void MMU_Disable_WTL(MMU_NAME_t mmu_name);
//-----------------------------------------------------------------------------
// NAME : Write_TLB_Entry
// DESCRIPTION : To load one item in the TLB, 5 consecutive rhea register
// accesses are required.
// This entry is loaded at the address pointed by the lock
// counter register.
// 1. Write CAM msb in CAM_REG_H register
// 2. Write CAM lsb in CAM_REG_L register
// 3. Write RAM msb in RAM_REG_H register
// 4. Write RAM lsb in RAM_REG_L register
// 5. Update Lock Counter register
// 6. Write 1 in LD_TLB_REG register
// PARAMETERS : mmu_name could be DSP_MMU
// LB_MMU
// HSAB_MMU
// physical_address
// virtual_address
// slst could be SECTION
// LARGE_PAGE
// SMALL_PAGE
// TINT_PAGE
// AP_bits could be NOT_ACCESSIBLE
// READ_ONLY
// FULL_ACCESS
// locked_base_value
// current_entry
// p_bit could be ENTRY_NOT_PRESERVED
// ENTRY_PRESERVED
// RETURN VALUE: None.
// LIMITATIONS : It is possible to load an entry in the TLB only if
// the WTL is DISABLED.
//-----------------------------------------------------------------------------
void MMU_Write_TLB_Entry(MMU_NAME_t mmu_name,
UWORD32 physical_address,
UWORD32 virtual_address,
SLST_t slst_bit,
AP_t ap_bits,
UWORD8 locked_base_value, // between 0 and 31
UWORD8 current_entry, // between base_value and 31
PRESERVED_t p_bit);
#endif /* _OMAP30_DSPMMU__H_ */
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