📄 omap30_mmu.h
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//DSPMMU_READ_CAM_H_REG
//-------------------
#define DSPMMU_READ_CAM_H_REG REG32(MEM_ARM_DSP_MMU_ADDR+0x44)
#define DSPMMU_READ_CAM_H_REG_READ_CAM_H_POS 0
#define DSPMMU_READ_CAM_H_REG_READ_CAM_H_NUMB 16
#define DSPMMU_READ_CAM_H_REG_READ_CAM_H_RES_VAL 0x0
//R/W
//DSPMMU_READ_CAM_L_REG
//-------------------
#define DSPMMU_READ_CAM_L_REG REG32(MEM_ARM_DSP_MMU_ADDR+0x48)
#define DSPMMU_READ_CAM_L_REG_VA_TAG_I2_POS 4
#define DSPMMU_READ_CAM_L_REG_VA_TAG_I2_NUMB 10
#define DSPMMU_READ_CAM_L_REG_VA_TAG_I2_RES_VAL 0x0
//R/W
#define DSPMMU_READ_CAM_L_REG_P_POS 3
#define DSPMMU_READ_CAM_L_REG_P_NUMB 1
#define DSPMMU_READ_CAM_L_REG_P_RES_VAL 0x0
//R/W
#define DSPMMU_READ_CAM_L_REG_V_POS 2
#define DSPMMU_READ_CAM_L_REG_V_NUMB 1
#define DSPMMU_READ_CAM_L_REG_V_RES_VAL 0x0
//R
#define DSPMMU_READ_CAM_L_REG_SLTS_POS 0
#define DSPMMU_READ_CAM_L_REG_SLTS_NUMB 2
#define DSPMMU_READ_CAM_L_REG_SLTS_RES_VAL 0x0
//R/W
//DSPMMU_READ_RAM_H_REG
//-------------------
#define DSPMMU_READ_RAM_H_REG REG32(MEM_ARM_DSP_MMU_ADDR+0x4C)
#define DSPMMU_READ_RAM_H_REG_READ_RAM_H_POS 0
#define DSPMMU_READ_RAM_H_REG_READ_RAM_H_NUMB 16
#define DSPMMU_READ_RAM_H_REG_READ_RAM_H_RES_VAL 0x0
//R/W
//DSPMMU_READ_RAM_L_REG
//-------------------
#define DSPMMU_READ_RAM_L_REG REG32(MEM_ARM_DSP_MMU_ADDR+0x50)
#define DSPMMU_READ_RAM_L_REG_RAM_LSB_POS 10
#define DSPMMU_READ_RAM_L_REG_RAM_LSB_NUMB 6
#define DSPMMU_READ_RAM_L_REG_RAM_LSB_RES_VAL 0x0
//R/W
#define DSPMMU_READ_RAM_L_REG_AP_POS 7
#define DSPMMU_READ_RAM_L_REG_AP_NUMB 3
#define DSPMMU_READ_RAM_L_REG_AP_RES_VAL 0x0
//R/W
#define LBMMU_BASE_ADDR MEM_ARM_LOCAL_BUS_MMU_ADDR
//LBMMU_PREFETCH_REG
//-------------------
#define LBMMU_PREFETCH_REG REG32(MEM_ARM_LOCAL_BUS_MMU_ADDR+0x00)
#define LBMMU_PREFETCH_REG_PORD_POS 14
#define LBMMU_PREFETCH_REG_PORD_NUMB 1
#define LBMMU_PREFETCH_REG_PORD_RES_VAL 0x0
//R/W
#define LBMMU_PREFETCH_REG_PREFETCH_POS 0
#define LBMMU_PREFETCH_REG_PREFETCH_NUMB 14
#define LBMMU_PREFETCH_REG_PREFETCH_RES_VAL 0x0
//R/W
//LBMMU_WALKING_ST_REG
//-------------------
#define LBMMU_WALKING_ST_REG REG32(MEM_ARM_LOCAL_BUS_MMU_ADDR+0x04)
#define LBMMU_WALKING_ST_REG_WTL_WORKING_POS 1
#define LBMMU_WALKING_ST_REG_WTL_WORKING_NUMB 1
#define LBMMU_WALKING_ST_REG_WTL_WORKING_RES_VAL 0x0
//R
#define LBMMU_WALKING_ST_REG_PREFETCH_WORKING_POS 0
#define LBMMU_WALKING_ST_REG_PREFETCH_WORKING_NUMB 1
#define LBMMU_WALKING_ST_REG_PREFETCH_WORKING_RES_VAL 0x0
//R
//LBMMU_CNTL_REG
//-------------------
#define LBMMU_CNTL_REG REG32(MEM_ARM_LOCAL_BUS_MMU_ADDR+0x08)
#define LBMMU_CNTL_REG_BURST_16MNGT_EN_POS 5
#define LBMMU_CNTL_REG_BURST_16MNGT_EN_NUMB 1
#define LBMMU_CNTL_REG_BURST_16MNGT_EN_RES_VAL 0x0
//R/W
#define LBMMU_CNTL_REG_WTL_EN_POS 2
#define LBMMU_CNTL_REG_WTL_EN_NUMB 1
#define LBMMU_CNTL_REG_WTL_EN_RES_VAL 0x0
//R/W
#define LBMMU_CNTL_REG_MMU_EN_POS 1
#define LBMMU_CNTL_REG_MMU_EN_NUMB 1
#define LBMMU_CNTL_REG_MMU_EN_RES_VAL 0x0
//R/W
#define LBMMU_CNTL_REG_RESET_SW_POS 0
#define LBMMU_CNTL_REG_RESET_SW_NUMB 1
#define LBMMU_CNTL_REG_RESET_SW_RES_VAL 0x0
//R/W
//LBMMU_FAULT_AD_H_REG
//-------------------
#define LBMMU_FAULT_AD_H_REG REG32(MEM_ARM_LOCAL_BUS_MMU_ADDR+0x0C)
#define LBMMU_FAULT_AD_H_REG_FAULT_AD_H_POS 0
#define LBMMU_FAULT_AD_H_REG_FAULT_AD_H_NUMB 16
#define LBMMU_FAULT_AD_H_REG_FAULT_AD_H_RES_VAL 0x0
//R
//LBMMU_FAULT_AD_L_REG
//-------------------
#define LBMMU_FAULT_AD_L_REG REG32(MEM_ARM_LOCAL_BUS_MMU_ADDR+0x10)
#define LBMMU_FAULT_AD_L_REG_FAULT_AD_L_POS 0
#define LBMMU_FAULT_AD_L_REG_FAULT_AD_L_NUMB 16
#define LBMMU_FAULT_AD_L_REG_FAULT_AD_L_RES_VAL 0x0
//R
//LBMMU_F_ST_REG
//-------------------
#define LBMMU_F_ST_REG REG32(MEM_ARM_LOCAL_BUS_MMU_ADDR+0x14)
#define LBMMU_F_ST_REG_PREFETCH_ERR_POS 3
#define LBMMU_F_ST_REG_PREFETCH_ERR_NUMB 1
#define LBMMU_F_ST_REG_PREFETCH_ERR_RES_VAL 0x0
//R
#define LBMMU_F_ST_REG_PERM_FAULT_POS 2
#define LBMMU_F_ST_REG_PERM_FAULT_NUMB 1
#define LBMMU_F_ST_REG_PERM_FAULT_RES_VAL 0x0
//R
#define LBMMU_F_ST_REG_TLB_MISS_POS 1
#define LBMMU_F_ST_REG_TLB_MISS_NUMB 1
#define LBMMU_F_ST_REG_TLB_MISS_RES_VAL 0x0
//R
#define LBMMU_F_ST_REG_TRANS_FAULT_POS 0
#define LBMMU_F_ST_REG_TRANS_FAULT_NUMB 1
#define LBMMU_F_ST_REG_TRANS_FAULT_RES_VAL 0x0
//R
//LBMMU_IT_ACK_REG
//-------------------
#define LBMMU_IT_ACK_REG REG32(MEM_ARM_LOCAL_BUS_MMU_ADDR+0x18)
#define LBMMU_IT_ACK_REG_IT_ACK_POS 0
#define LBMMU_IT_ACK_REG_IT_ACK_NUMB 1
#define LBMMU_IT_ACK_REG_IT_ACK_RES_VAL 0x0
//W
//LBMMU_TTB_H_REG
//-------------------
#define LBMMU_TTB_H_REG REG32(MEM_ARM_LOCAL_BUS_MMU_ADDR+0x1C)
#define LBMMU_TTB_H_REG_TTB_H_REG_POS 0
#define LBMMU_TTB_H_REG_TTB_H_REG_NUMB 16
#define LBMMU_TTB_H_REG_TTB_H_REG_RES_VAL 0x0
//R/W
//LBMMU_TTB_L_REG
//-------------------
#define LBMMU_TTB_L_REG REG32(MEM_ARM_LOCAL_BUS_MMU_ADDR+0x20)
#define LBMMU_TTB_L_REG_TTB_L_POS 7
#define LBMMU_TTB_L_REG_TTB_L_NUMB 9
#define LBMMU_TTB_L_REG_TTB_L_RES_VAL 0x0
//R/W
//LBMMU_LOCK_REG
//-------------------
#define LBMMU_LOCK_REG REG32(MEM_ARM_LOCAL_BUS_MMU_ADDR+0x24)
#define LBMMU_LOCK_REG_BASE_VALUE_POS 10
#define LBMMU_LOCK_REG_BASE_VALUE_NUMB 6
#define LBMMU_LOCK_REG_BASE_VALUE_RES_VAL 0x0
//R/W
#define LBMMU_LOCK_REG_CURRENT_VICTIM_POS 4
#define LBMMU_LOCK_REG_CURRENT_VICTIM_NUMB 6
#define LBMMU_LOCK_REG_CURRENT_VICTIM_RES_VAL 0x0
//R/W
//LBMMU_LD_TLB_REG
//-------------------
#define LBMMU_LD_TLB_REG REG32(MEM_ARM_LOCAL_BUS_MMU_ADDR+0x28)
#define LBMMU_LD_TLB_REG_LD_TLB_ITEM_POS 0
#define LBMMU_LD_TLB_REG_LD_TLB_ITEM_NUMB 1
#define LBMMU_LD_TLB_REG_LD_TLB_ITEM_RES_VAL 0x0
//R/W
//LBMMU_CAM_H_REG
//-------------------
#define LBMMU_CAM_H_REG REG32(MEM_ARM_LOCAL_BUS_MMU_ADDR+0x2C)
#define LBMMU_CAM_H_REG_VA_TAG_LL_H_POS 0
#define LBMMU_CAM_H_REG_VA_TAG_LL_H_NUMB 16
#define LBMMU_CAM_H_REG_VA_TAG_LL_H_RES_VAL 0x0
//R/W
//LBMMU_CAM_L_REG
//-------------------
#define LBMMU_CAM_L_REG REG32(MEM_ARM_LOCAL_BUS_MMU_ADDR+0x30)
#define LBMMU_CAM_L_REG_VA_TAGL1_L_POS 14
#define LBMMU_CAM_L_REG_VA_TAGL1_L_NUMB 2
#define LBMMU_CAM_L_REG_VA_TAGL1_L_RES_VAL 0x0
//R/W
#define LBMMU_CAM_L_REG_VA_TAG_I2_POS 4
#define LBMMU_CAM_L_REG_VA_TAG_I2_NUMB 10
#define LBMMU_CAM_L_REG_VA_TAG_I2_RES_VAL 0x0
//R/W
#define LBMMU_CAM_L_REG_P_POS 3
#define LBMMU_CAM_L_REG_P_NUMB 1
#define LBMMU_CAM_L_REG_P_RES_VAL 0x0
//R/W
#define LBMMU_CAM_L_REG_V_POS 2
#define LBMMU_CAM_L_REG_V_NUMB 1
#define LBMMU_CAM_L_REG_V_RES_VAL 0x0
//R
#define LBMMU_CAM_L_REG_SLTS_POS 0
#define LBMMU_CAM_L_REG_SLTS_NUMB 2
#define LBMMU_CAM_L_REG_SLTS_RES_VAL 0x0
//R/W
//LBMMU_RAM_H_REG
//-------------------
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