📄 omap30.h
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//-------------------------------------------------------------------------------
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
//
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work.
// Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved.
//
//-------------------------------------------------------------------------------
#ifndef _OMAP30__H_
#define _OMAP30__H_
//-------------------------------------------------------------------------------
//
// COMMON LIBRARY INCLUDES
//
//-------------------------------------------------------------------------------
#include "global_types.h"
#include "arm925t.h"
#include "omap30_tcif.h"
#include "omap30_clkrst.h"
#include "omap30_sysdma.h"
#include "omap30_lcdc.h"
#include "omap30_system_init.h"
#include "omap30_armwdg.h"
#include "omap30_armgpio.h"
#include "omap30_apif.h"
#include "omap30_armmbx.h"
#include "omap30_arminth.h"
#include "omap30_mmu.h"
//-------------------------------------------------------------------------------
//
// COMMON FUNCTIONNAL DEFINES
//
//-------------------------------------------------------------------------------
// DPLL_COMMON_MULTIPLIER in range 2-31
#define DPLL_COMMON_MULTIPLIER (UWORD8)25
// DPLL_COMMON_DIVIDER in range 1-4
#define DPLL_COMMON_DIVIDER (UWORD8)2
// REFERENCE CLOCK (INPUT)
#define INPUT_CHIP_FREQUENCY 12000000
//-------------------------------------------------------------------------------
//
// OMAP3.0 MEMORY MAPPING
//
//-------------------------------------------------------------------------------
// SLOW, FAST AND INTERNAL SRAM MEMORY INTERFACES MAPPING
#define MEM_MIF_CS0_ADDRESS 0x00000000
#define MEM_MIF_CS0_LENGTH 0x02000000
#define MEM_MIF_CS1_ADDRESS 0x04000000
#define MEM_MIF_CS1_LENGTH 0x02000000
#define MEM_MIF_CS2_ADDRESS 0x08000000
#define MEM_MIF_CS2_LENGTH 0x02000000
#define MEM_MIF_CS3_ADDRESS 0x0C000000
#define MEM_MIF_CS3_LENGTH 0x02000000
#define MEM_MIF_CS4_ADDRESS 0x10000000
#define MEM_MIF_CS4_LENGTH 0x0C000000
#define MEM_MIF_CS6_ADDRESS 0x20000000
#define MEM_MIF_CS6_LENGTH 0x00080000
// ARM RHEA PERIPHERALS MAPPING
#define ARM_PUBLIC_RHEA_STROBE_0 0xFFFB0000
#define ARM_PUBLIC_RHEA_STROBE_1 0xFFFC0000
#define ARM_PRIVATE_RHEA_STROBE_0 0xFFFD0000
#define ARM_PRIVATE_RHEA_STROBE_1 0xFFFE0000
#define DSP_SHARED_RHEA_STROBE_0 0xE1000000
#define DSP_SHARED_RHEA_STROBE_1 0xE1010000
#define RHEA_OFFSET_CS0 0x0000
#define RHEA_OFFSET_CS1 0x0800
#define RHEA_OFFSET_CS2 0x1000
#define RHEA_OFFSET_CS3 0x1800
#define RHEA_OFFSET_CS4 0x2000
#define RHEA_OFFSET_CS5 0x2800
#define RHEA_OFFSET_CS6 0x3000
#define RHEA_OFFSET_CS7 0x3800
#define RHEA_OFFSET_CS8 0x4000
#define RHEA_OFFSET_CS9 0x4800
#define RHEA_OFFSET_CS10 0x5000
#define RHEA_OFFSET_CS11 0x5800
#define RHEA_OFFSET_CS12 0x6000
#define RHEA_OFFSET_CS13 0x6800
#define RHEA_OFFSET_CS14 0x7000
#define RHEA_OFFSET_CS15 0x7800
#define RHEA_OFFSET_CS16 0x8000
#define RHEA_OFFSET_CS17 0x8800
#define RHEA_OFFSET_CS18 0x9000
#define RHEA_OFFSET_CS19 0x9800
#define RHEA_OFFSET_CS20 0xA000
#define RHEA_OFFSET_CS21 0xA800
#define RHEA_OFFSET_CS22 0xB000
#define RHEA_OFFSET_CS23 0xB800
#define RHEA_OFFSET_CS24 0xC000
#define RHEA_OFFSET_CS25 0xC800
#define RHEA_OFFSET_CS26 0xD000
#define RHEA_OFFSET_CS27 0xD800
#define RHEA_OFFSET_CS28 0xE000
#define RHEA_OFFSET_CS29 0xE800
#define RHEA_OFFSET_CS30 0xF000
#define RHEA_OFFSET_CS31 0xF800
#define MEM_ARM_GPIO_ADDR (ARM_PUBLIC_RHEA_STROBE_1 + RHEA_OFFSET_CS28)
#define MEM_ARM_UART_ADDR (ARM_PUBLIC_RHEA_STROBE_1 + RHEA_OFFSET_CS29)
#define MEM_ARM_MAILBOX_ADDR (ARM_PUBLIC_RHEA_STROBE_1 + RHEA_OFFSET_CS30)
#define BASE_ADDRESS_INT_PERI (ARM_PRIVATE_RHEA_STROBE_1+RHEA_OFFSET_CS24)
#define MEM_SIZE_IN_BYTES 0x100
#define MEM_ARM_LCD_CONTROLLER_ADDR (BASE_ADDRESS_INT_PERI)
#define MEM_ARM_LOCALBUS_ADDR (BASE_ADDRESS_INT_PERI + 1*MEM_SIZE_IN_BYTES)
#define MEM_ARM_LOCAL_BUS_MMU_ADDR (BASE_ADDRESS_INT_PERI + 2*MEM_SIZE_IN_BYTES)
#define MEM_ARM_HSAB_INTERFACE_ADDR (BASE_ADDRESS_INT_PERI + 3*MEM_SIZE_IN_BYTES)
#define MEM_ARM_HSAB_MMU_ADDR (BASE_ADDRESS_INT_PERI + 4*MEM_SIZE_IN_BYTES)
#define MEM_ARM_TIMER_1_ADDR (BASE_ADDRESS_INT_PERI + 5*MEM_SIZE_IN_BYTES)
#define MEM_ARM_TIMER_2_ADDR (BASE_ADDRESS_INT_PERI + 6*MEM_SIZE_IN_BYTES)
#define MEM_ARM_TIMER_3_ADDR (BASE_ADDRESS_INT_PERI + 7*MEM_SIZE_IN_BYTES)
#define MEM_ARM_WDG_TIMER_ADDR (BASE_ADDRESS_INT_PERI + 8*MEM_SIZE_IN_BYTES)
#define MEM_ARM_API_INTERFACE_ADDR (BASE_ADDRESS_INT_PERI + 9*MEM_SIZE_IN_BYTES)
#define MEM_ARM_RHEA_PRIV__ADDR (BASE_ADDRESS_INT_PERI + 10*MEM_SIZE_IN_BYTES)
#define MEM_ARM_INTH_ADDR (BASE_ADDRESS_INT_PERI + 11*MEM_SIZE_IN_BYTES)
#define MEM_ARM_TC_ADDR (BASE_ADDRESS_INT_PERI + 12*MEM_SIZE_IN_BYTES)
#define MEM_ARM_CLKM_ADDR (BASE_ADDRESS_INT_PERI + 14*MEM_SIZE_IN_BYTES)
#define MEM_ARM_DPLL1_ADDR (BASE_ADDRESS_INT_PERI + 15*MEM_SIZE_IN_BYTES)
#define MEM_ARM_DPLL2_ADDR (BASE_ADDRESS_INT_PERI + 16*MEM_SIZE_IN_BYTES)
#define MEM_ARM_DPLL3_ADDR (BASE_ADDRESS_INT_PERI + 17*MEM_SIZE_IN_BYTES)
#define MEM_ARM_DSP_MMU_ADDR (BASE_ADDRESS_INT_PERI + 18*MEM_SIZE_IN_BYTES)
#define MEM_ARM_RHEA_PUB_ADDR (BASE_ADDRESS_INT_PERI + 19*MEM_SIZE_IN_BYTES)
#define MEM_ARM_JTAG_ID_CODE_ADDR (BASE_ADDRESS_INT_PERI + 20*MEM_SIZE_IN_BYTES)
#define MEM_ARM_DMA_CONTROLLER_ADDR (BASE_ADDRESS_INT_PERI + 24*MEM_SIZE_IN_BYTES)
// DSP SHARED RHEA PERIPHERALS MAPPING
#define MEM_DSP_GPIO_ADDR (DSP_SHARED_RHEA_STROBE_1 + RHEA_OFFSET_CS28)
#define MEM_DSP_UART_ADDR (DSP_SHARED_RHEA_STROBE_1 + RHEA_OFFSET_CS29)
#define MEM_DSP_MB_ADDR (DSP_SHARED_RHEA_STROBE_1 + RHEA_OFFSET_CS30)
#define MEM_DSP_CLKM_ADDR (DSP_SHARED_RHEA_STROBE_0 + RHEA_OFFSET_CS16)
#define MEM_DSP_DSPMMU_ADDR (DSP_SHARED_RHEA_STROBE_0 + RHEA_OFFSET_CS17)
//-------------------------------------------------------------------------------
//
// OMAP3.0 INTERRUPT MAPPING
//
//-------------------------------------------------------------------------------
#define EXTERNAL_0_INT INTH_INDEX_0
//chenyue 2003/04/08 for camera debugging, in spec, camera use interrupt 1
//#define EXTERNAL_1_INT INTH_INDEX_1
#define CAMERA_INT INTH_INDEX_1
#define EXTERNAL_2_INT INTH_INDEX_2
#define EXTERNAL_3_INT INTH_INDEX_3
#define EXTERNAL_4_INT INTH_INDEX_4
#define EXTERNAL_5_INT INTH_INDEX_5
#define EXTERNAL_6_INT INTH_INDEX_6
#define EXTERNAL_7_INT INTH_INDEX_7
#define EXTERNAL_8_INT INTH_INDEX_8
#define ABORT_INT INTH_INDEX_9
#define DSP_MAILBOX1_INT INTH_INDEX_10
#define DSP_MAILBOX2_INT INTH_INDEX_11
#define HSB_MAILBOX_INT INTH_INDEX_12
#define RHEA_BRIDGE1_INT INTH_INDEX_13
#define GPIO_INT INTH_INDEX_14
#define UART_INT INTH_INDEX_15
#define TIMER3_INT INTH_INDEX_16
#define LB_MMU_INT INTH_INDEX_17
#define HSAB_MMU_INT INTH_INDEX_18
#define DMA_CH0_INT INTH_INDEX_19
#define DMA_CH1_INT INTH_INDEX_20
#define DMA_CH2_INT INTH_INDEX_21
#define DMA_CH3_INT INTH_INDEX_22
#define DMA_CH4_INT INTH_INDEX_23
#define DMA_CH5_INT INTH_INDEX_24
#define DMA_CH_LCD_INT INTH_INDEX_25
#define TIMER1_INT INTH_INDEX_26
#define WD_TIMER_INT INTH_INDEX_27
#define RHEA_BRIDGE2_INT INTH_INDEX_28
#define LOCAL_BUS_IF_INT INTH_INDEX_29
#define TIMER2_INT INTH_INDEX_30
#define LCD_CTRL_INT INTH_INDEX_31
#endif /* _OMAP30__H_ */
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