omap1510_inth2.c

有关于USB的一些主机端驱动

//===============================================================================
//            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
//                                                                             
//   Property of Texas Instruments 
//   For  Unrestricted  Internal  Use  Only 
//   Unauthorized reproduction and/or distribution is strictly prohibited.  
//   This product is protected under copyright law and trade secret law 
//   as an unpublished work.  
//   Created 2000, (C) Copyright 1999 Texas Instruments.  All rights reserved.
//
//===============================================================================
#include "omap30.h"
#include "omap30_arminth.h"
#include "omap1510_inth2.h"
#include "omap1510_inth_mapping.h"
#include "omap1510.h"

//############################################################################
// NAME        : INTH2_InitLevel                                                   
//
// DESCRIPTION : Writes Level Register (Mask or Unmask interrupt)
//
// PARAMETERS  : UWORD8   ItIndex        See int_mapping.h
//
//               BOOL     Fiq_or_Irq    INTH_FIQ or INTH_IRQ
//
//               UWORD8   Priority      from 0 to 15
//
//               BOOL     SensitiveEdge FALLING_EDGE_SENSITIVE or LOW_LEVEL_SENSITIVE
//
// RETURN VALUE: None
//
// LIMITATIONS : None                                                        
//############################################################################
void INTH2_InitLevel (UWORD8   ItIndex, 
                      BOOL     Fiq_or_Irq,
                      UWORD8   Priority,
                      BOOL     SensitiveEdge)
{
  // Point to the  OrderedITNumber 
  volatile UWORD32* PtLevelReg;
   
  if(ItIndex<32) // First level interrupt handler
    {
    /*PtLevelReg = (UWORD32*)INTH_IT_LEVEL_REG_SUPERVISOR_ADDR + ItIndex;
    *PtLevelReg = (  (Fiq_or_Irq <<LEV1_INTH_FIQNIRQ_POSBIT)
                   | (Priority      <<LEV1_INTH_PRIORITY_POSBIT) 
                   | (SensitiveEdge <<LEV1_INTH_SENSITIVE_EDGE_POSBIT));*/
    /*ARMINTH_ILRx(ItIndex) = ( (Fiq_or_Irq    << ARMINTH_ILRx_FIQ_POS)
                            | (Priority      << ARMINTH_ILRx_PRIORITY_POS) 
                            | (SensitiveEdge << ARMINTH_ILRx_SENS_EDGE_POS));*/
	PtLevelReg = (UWORD32*)ARMINTH_ILRx_ADD + ItIndex;
	*PtLevelReg = ( (Fiq_or_Irq    << ARMINTH_ILRx_FIQ_POS)
                  | (Priority      << ARMINTH_ILRx_PRIORITY_POS) 
                  | (SensitiveEdge << ARMINTH_ILRx_SENS_EDGE_POS));

    }
  else
    {
    /*PtLevelReg = (UWORD32*)LEV2_INTH_IT_LEVEL_REG_SUPERVISOR_ADDR + (ItIndex-32);
    *PtLevelReg = (  (Fiq_or_Irq << LEV2_INTH_FIQNIRQ_POSBIT)
                   | (Priority      << LEV2_INTH_PRIORITY_POSBIT) 
                   | (SensitiveEdge << LEV2_INTH_SENSITIVE_EDGE_POSBIT));*/
    /*LEV2_INTH_ILRx(ItIndex-32) = ( (Fiq_or_Irq    << LEV2_INTH_ILRx_FIQ_POS)
                                 | (Priority      << LEV2_INTH_ILRx_FIQ_POS) 
                                 | (SensitiveEdge << LEV2_INTH_ILRx_FIQ_POS));*/

    PtLevelReg = (UWORD32*)LEV2_INTH_ILRx_ADD + (ItIndex-32);
    *PtLevelReg = ( (Fiq_or_Irq    << LEV2_INTH_ILRx_FIQ_POS)
                  | (Priority      << LEV2_INTH_ILRx_PRIORITY_POS) 
                  | (SensitiveEdge << LEV2_INTH_ILRx_SENS_EDGE_POS));

	
	if (Fiq_or_Irq == INTH_IRQ)
      {
/*	PtLevelReg = (UWORD32*)INTH_IT_LEVEL_REG_SUPERVISOR_ADDR + LEV2_IRQ_INT;
	*PtLevelReg = (  (Fiq_or_Irq <<LEV1_INTH_FIQNIRQ_POSBIT)
                   | (Priority      <<LEV1_INTH_PRIORITY_POSBIT) 
                   | (SensitiveEdge <<LEV1_INTH_SENSITIVE_EDGE_POSBIT));*/	
    /*ARMINTH_ILRx(LEV2_IRQ_INT) = ( (Fiq_or_Irq    << ARMINTH_ILRx_FIQ_POS)
                                 | (Priority      << ARMINTH_ILRx_PRIORITY_POS) 
                                 | (SensitiveEdge << ARMINTH_ILRx_SENS_EDGE_POS));*/
	
	PtLevelReg = (UWORD32*)ARMINTH_ILRx_ADD + LEV2_IRQ_INT;
	*PtLevelReg = ( (Fiq_or_Irq    << ARMINTH_ILRx_FIQ_POS)
                  | (Priority      << ARMINTH_ILRx_PRIORITY_POS) 
                  | (SensitiveEdge << ARMINTH_ILRx_SENS_EDGE_POS));

	
	}
    else
      { 
/*	PtLevelReg = (UWORD32*)INTH_IT_LEVEL_REG_SUPERVISOR_ADDR + LEV2_FIQ_INT;
	*PtLevelReg = (  (Fiq_or_Irq <<LEV1_INTH_FIQNIRQ_POSBIT)
                   | (Priority      <<LEV1_INTH_PRIORITY_POSBIT) 
                   | (SensitiveEdge <<LEV1_INTH_SENSITIVE_EDGE_POSBIT));*/
    /*ARMINTH_ILRx(LEV2_FIQ_INT) = ( (Fiq_or_Irq    << ARMINTH_ILRx_FIQ_POS)
                                 | (Priority      << ARMINTH_ILRx_PRIORITY_POS) 
                                 | (SensitiveEdge << ARMINTH_ILRx_SENS_EDGE_POS));*/	
	PtLevelReg = (UWORD32*)ARMINTH_ILRx_ADD + LEV2_FIQ_INT;
	*PtLevelReg = ( (Fiq_or_Irq    << ARMINTH_ILRx_FIQ_POS)
                  | (Priority      << ARMINTH_ILRx_PRIORITY_POS) 
                  | (SensitiveEdge << ARMINTH_ILRx_SENS_EDGE_POS));

      }
    }
}

/*
//########################################################################################
// NAME        : INTH2_GetCurrentIt                                                 
//
// DESCRIPTION : Get the current It and valid the next one
//              
//
// PARAMETERS  : Fiq_or_Irq:  INTH_IRQ or INTH_FIQ
//
//
// RETURN VALUE: Number of the active and acknowledged Interrupt          
//
// LIMITATIONS : Must be called on Incoming IT                            
//########################################################################################
UWORD8 INTH2_GetCurrentIt (BOOL Fiq_or_Irq)
{
UWORD8 ActivItIndex;

  if (Fiq_or_Irq == INTH_IRQ)
     {
     ActivItIndex=(*(UWORD8 *)(ARMINTH_SIR_IRQ_CODE_REG))&ARMINTH_SIR_IRQ_CODE_IRQ_NUM_MASK;
     
     //Test if the interrupt comes from the second handler
     if (ActivItIndex==LEV2_IRQ_INT)
         {
         ActivItIndex=(*(UWORD8 *)(LEV2_INTH_SIR_IRQ_CODE_REG))&LEV2_INTH_SIR_IRQ_CODE_IRQ_NUM_MASK;
         ActivItIndex=ActivItIndex+32;
 
         }

     }
  else// INTH_FIQ
     {
     ActivItIndex=(*(UWORD8 *)(ARMINTH_SIR_FIQ_CODE_REG))&ARMINTH_SIR_FIQ_CODE_FIQ_NUM_MASK;
     
     //Test if the interrupt comes from the second handler
     if (ActivItIndex==LEV2_FIQ_INT)
         {
         ActivItIndex=(*(UWORD8 *)(LEV2_INTH_SIR_FIQ_CODE_REG))&LEV2_INTH_SIR_FIQ_CODE_FIQ_NUM_MASK;
         ActivItIndex=ActivItIndex+32;
        
         }

     }

  return(ActivItIndex);
}

//########################################################################################
// NAME        : INTH2_ValidNextInterrupt                                                 
//
// DESCRIPTION : Valid the next IT depending on the current one 
//              
//
// PARAMETERS  : Fiq_or_Irq:  INTH_IRQ or INTH_FIQ
//
//
// RETURN VALUE: None       
//
// LIMITATIONS : Must be called on Incoming IT                            
//########################################################################################
void INTH2_ValidNextInterrupt (BOOL Fiq_or_Irq)
{
UWORD16 ActivItIndex;

  if (Fiq_or_Irq == INTH_IRQ)
     {
     ActivItIndex=(*(UWORD8 *)(ARMINTH_SIR_IRQ_CODE_REG))&ARMINTH_SIR_IRQ_CODE_IRQ_NUM_MASK;
     

     //Test if the interrupt comes from the second handler
     if (ActivItIndex==LEV2_IRQ_INT)
         {
         //read the register to aknowledge the interrupt
         ActivItIndex=(*(UWORD8 *)(LEV2_INTH_SIR_IRQ_CODE_REG))&LEV2_INTH_SIR_IRQ_CODE_IRQ_NUM_MASK;
         
         //Clear the ITR register
         ClearBitIndex(REG32(LEV2_INTH_ITR_REG),ActivItIndex);

         //Valid next Irq on handler2
         SetBitIndex(REG32(LEV2_INTH_CONTROL_REG_REG),Fiq_or_Irq);
         }

    //Clear the ITR register
    ClearBitIndex(REG32(ARMINTH_ITR_REG),ActivItIndex);

     //Valid next Irq on handler1
     SetBitIndex(REG32(ARMINTH_CONTROL_REG_REG),Fiq_or_Irq);
     }
  else// INTH_FIQ
     {
     ActivItIndex=(*(UWORD8 *)(ARMINTH_SIR_FIQ_CODE_REG))&ARMINTH_SIR_FIQ_CODE_FIQ_NUM_MASK;
     
     //Test if the interrupt comes from the second handler
     if (ActivItIndex==LEV2_FIQ_INT)
         {
         //read the register to aknowledge the interrupt
         ActivItIndex=(*(UWORD8 *)(LEV2_INTH_SIR_FIQ_CODE_REG))&LEV2_INTH_SIR_FIQ_CODE_FIQ_NUM_MASK;

         //Clear the ITR register
         ClearBitIndex(REG32(LEV2_INTH_ITR_REG),ActivItIndex);

         //Valid next Irq on handler2
         SetBitIndex(REG32(LEV2_INTH_CONTROL_REG_REG),Fiq_or_Irq);
         }

    //Clear the ITR register
     ClearBitIndex(REG32(ARMINTH_ITR_REG),ActivItIndex);

     //Valid next Irq on handler1
     SetBitIndex(REG32(ARMINTH_CONTROL_REG_REG),Fiq_or_Irq);
     }

}


//########################################################################################
// NAME        : INTH2_ClearInt                                                 
//
// DESCRIPTION : Clear the an IT when IT is not enabled (outside of a routine) 
//               Prefer use ValidNext in a routine 
//               
//
// PARAMETERS  : ItNumber
//
//
// RETURN VALUE: None       
//
// LIMITATIONS : None                            
//########################################################################################
void INTH2_ClearInt(UWORD8 ItIndex)
{
//UWORD16 ActivItIndex;

     //Test if the interrupt comes from the second handler
     if (ItIndex>31)
         {
         //Clear the ITR register
         ClearBitIndex(REG32(LEV2_INTH_ITR_REG),(ItIndex-32));
         }
     else
         {
         //Clear the ITR register
         ClearBitIndex(REG32(ARMINTH_ITR_REG),ItIndex);
         }


}
*/
//########################################################################################
// NAME        : INTH2_EnableOneIT                                                 
//
// DESCRIPTION : Enable one interrupt                              
//
// PARAMETERS  : UWORD8 ItIndex                      See int_mapping.h
//
//              Fiq_or_Irq:  INTH_IRQ or INTH_FIQ
//
// RETURN VALUE: None         
//
// LIMITATIONS : Must be called on Incoming IT                            
//########################################################################################
void INTH2_EnableOneIT(UWORD8 ItIndex, BOOL Fiq_or_Irq)
{
  if(ItIndex<32)
    {
         //Clear the ITR register         
    ClearBitIndex(REG32(ARMINTH_ITR_REG),(ItIndex));
    ClearBitIndex(REG32(ARMINTH_MIR_REG),ItIndex);
    }
  else
    {
         //Clear the ITR register         
    ClearBitIndex(REG32(LEV2_INTH_ITR_REG),(ItIndex-32));
    ClearBitIndex(REG32(LEV2_INTH_MIR_REG),(ItIndex-32));
    if (Fiq_or_Irq==INTH_FIQ)
      {
      ClearBitIndex(REG32(ARMINTH_MIR_REG),LEV2_FIQ_INT);
      }
    else
      {
      ClearBitIndex(REG32(ARMINTH_MIR_REG),LEV2_IRQ_INT);
      }
    }
}


//########################################################################################
// NAME        : INTH2_DisableOneIT                                                 
//
// DESCRIPTION : Disable one interrupt                              
//
// PARAMETERS  : UWORD8 ItIndex 
//
// RETURN VALUE: None         
//
// LIMITATIONS : None                            
//########################################################################################
void INTH2_DisableOneIT(UWORD32 ItIndex)
{
  if(ItIndex<32)
    {
    *(UWORD32*)ARMINTH_MIR_REG |= (1 << ItIndex);
    }
  else
    {
    *(UWORD32*)LEV2_INTH_MIR_REG |= (1 << (ItIndex-32));
    // if the level 2 mask is FFFFFFFF then we can disable the it 0 and 1 on the 1st it handler
    if(REG32(LEV2_INTH_MIR_REG)==LEV2_INTH_MIR_IRQ_MSK_RES_VAL)
       {
	 *(UWORD32*)ARMINTH_MIR_REG |= (1 << LEV2_FIQ_INT);
	 *(UWORD32*)ARMINTH_MIR_REG |= (1 << LEV2_IRQ_INT);
       }
    }
}