omap30_mmu.c

有关于USB的一些主机端驱动

//-------------------------------------------------------------------------------
//          TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION  
//   Property of Texas Instruments
//   For Unrestricted Internal Use Only
//   Unauthorized reprofuction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work
//   Created 2000,  (C) Copyright 2000 Texas Instruments. All rights reserved
//
//------------------------------------------------------------------------------
#include "omap30.h"

//-------------------------------------------------------------------------------
//
//  FUNCTIONS
//
//-------------------------------------------------------------------------------

//-------------------------------------------------------------------------------
//  NAME	: MMU_Reset
//  DESCRIPTION : Resets the module. The module comes back to default config
//  PARAMETERS  : mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU
//  RETURN VALUE: None.
//  LIMITATIONS : None.
//-------------------------------------------------------------------------------
void MMU_Reset(MMU_NAME_t mmu_name)
{ 
    switch(mmu_name) 
    { 
    case HSAB_MMU : 
      { 
	ClearBitIndex(HSABMMU_CNTL_REG,HSABMMU_CNTL_REG_RESET_SW_POS); break; 
      } 
    case LB_MMU : 
      { 
	ClearBitIndex(LBMMU_CNTL_REG,LBMMU_CNTL_REG_RESET_SW_POS); break; 
      } 
    case DSP_MMU : 
      { 
	ClearBitIndex(DSPMMU_CNTL_REG,DSPMMU_CNTL_REG_RESET_SW_POS); break; 
      } 
    } 
}

//------------------------------------------------------------------------------- 
//  NAME	: MMU_Release_Reset
//  DESCRIPTION : Release Reset of module.
//  PARAMETERS  : mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU
//  RETURN VALUE: None.
//  LIMITATIONS : None.                                                      
//-------------------------------------------------------------------------------
void MMU_Release_Reset(MMU_NAME_t mmu_name)
{ 
    switch(mmu_name) 
    { 
    case HSAB_MMU : 
      { 
	SetBitIndex(HSABMMU_CNTL_REG,HSABMMU_CNTL_REG_RESET_SW_POS); break; 
      } 
    case LB_MMU : 
      { 
	SetBitIndex(LBMMU_CNTL_REG,LBMMU_CNTL_REG_RESET_SW_POS); break; 
      } 
    case DSP_MMU : 
      { 
	SetBitIndex(DSPMMU_CNTL_REG,DSPMMU_CNTL_REG_RESET_SW_POS); break; 
      } 
    } 
}

//-------------------------------------------------------------------------------
//  NAME	: MMU_Enable
//  DESCRIPTION : Enables MMU
//  PARAMETERS  : mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU
//  RETURN VALUE: None.
//  LIMITATIONS : None.
//-------------------------------------------------------------------------------
void MMU_Enable(MMU_NAME_t mmu_name)
{
    switch(mmu_name) 
    { 
    case HSAB_MMU : 
      { 
	SetBitIndex(HSABMMU_CNTL_REG,HSABMMU_CNTL_REG_MMU_EN_POS); break; 
      }
    case LB_MMU : 
      { 
	SetBitIndex(LBMMU_CNTL_REG,LBMMU_CNTL_REG_MMU_EN_POS); break; 
      } 
    case DSP_MMU : 
      { 
	SetBitIndex(DSPMMU_CNTL_REG,DSPMMU_CNTL_REG_MMU_EN_POS); break; 
      } 
    } 
}

//-------------------------------------------------------------------------------
//  NAME	: MMU_Disable
//  DESCRIPTION : Disables MMU
//  PARAMETERS  : mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU
//  RETURN VALUE: None.
//  LIMITATIONS : None.
//-------------------------------------------------------------------------------
void MMU_Disable(MMU_NAME_t mmu_name)
{ 
    switch(mmu_name) 
    { 
    case HSAB_MMU : 
      { 
	ClearBitIndex(HSABMMU_CNTL_REG,HSABMMU_CNTL_REG_MMU_EN_POS); break; 
      } 
    case LB_MMU : 
      { 
	ClearBitIndex(LBMMU_CNTL_REG,LBMMU_CNTL_REG_MMU_EN_POS); break; 
      } 
    case DSP_MMU : 
      { 
	ClearBitIndex(DSPMMU_CNTL_REG,DSPMMU_CNTL_REG_MMU_EN_POS); break; 
      } 
    } 
}

//-------------------------------------------------------------------------------
//  NAME	: MMU_Enable_WTL
//  DESCRIPTION : Enables Walking Table Logic
//  PARAMETERS  : mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU
//  RETURN VALUE: None.
//  LIMITATIONS : None.
//-------------------------------------------------------------------------------
void MMU_Enable_WTL(MMU_NAME_t mmu_name)
{ 
    switch(mmu_name) 
    { 
    case HSAB_MMU : 
      { 
	SetBitIndex(HSABMMU_CNTL_REG,HSABMMU_CNTL_REG_WTL_EN_POS); break; 
      }
    case LB_MMU : 
      { 
	SetBitIndex(LBMMU_CNTL_REG,LBMMU_CNTL_REG_WTL_EN_POS); break; 
      } 
    case DSP_MMU : 
      { 
	SetBitIndex(DSPMMU_CNTL_REG,DSPMMU_CNTL_REG_WTL_EN_POS); break;     
	} 
    } 
}

//-------------------------------------------------------------------------------
//  NAME	: MMU_Disable_WTL
//  DESCRIPTION : Disables Walking Table Logic
//  PARAMETERS  : mmu_name could be DSP_MMU or LB_MMU or HSAB_MMU
//  RETURN VALUE: None.
//  LIMITATIONS : None.                                                     
//-------------------------------------------------------------------------------
void MMU_Disable_WTL(MMU_NAME_t mmu_name)
{ 
    switch(mmu_name)
    { 
    case HSAB_MMU : 
      { 
	ClearBitIndex(HSABMMU_CNTL_REG,HSABMMU_CNTL_REG_WTL_EN_POS); break; 
      }
    case LB_MMU : 
      { 
	ClearBitIndex(LBMMU_CNTL_REG,LBMMU_CNTL_REG_WTL_EN_POS); break; 
      } 
    case DSP_MMU : 
      { 
	ClearBitIndex(DSPMMU_CNTL_REG,DSPMMU_CNTL_REG_WTL_EN_POS); break;     
	} 
    } 
}

//-----------------------------------------------------------------------------
// NAME        : MMU_Write_TLB_Entry                                             
// DESCRIPTION : To load one item in the TLB, 5 consecutive rhea register    
//               accesses are required.                                      
//               This entry is loaded at the address pointed by the lock     
//              counter register.                                           
//               1. Write CAM msb in CAM_REG_H register                      
//               2. Write CAM lsb in CAM_REG_L register                      
//               3. Write RAM msb in RAM_REG_H register                      
//               4. Write RAM lsb in RAM_REG_L register                      
//               5. Update Lock Counter register                             
//               6. Write 1 in LD_TLB_REG register                           
// PARAMETERS  : mmu_name could be DSP_MMU                                   
//                                LB_MMU                                    
//                                 HSAB_MMU                                  
//               physical_address                                            
//               virtual_address                                             
//               slst could be SECTION                                       
//			       LARGE_PAGE
//			       SMALL_PAGE
//			       TINT_PAGE
//		 AP_bits could be NOT_ACCESSIBLE
//				  READ_ONLY
//				  FULL_ACCESS
//		 locked_base_value
//		 current_entry
//		 p_bit could be ENTRY_NOT_PRESERVED
//				ENTRY_PRESERVED
// RETURN VALUE: None.                                                       
// LIMITATIONS : It is possible to load an entry in the TLB only if          
//               the WTL is DISABLED.                                        
//-----------------------------------------------------------------------------
void MMU_Write_TLB_Entry(MMU_NAME_t  mmu_name,
		     UWORD32     physical_address,
		     UWORD32     virtual_address,
		     SLST_t      slst_bit,
		     AP_t        ap_bits,
		     UWORD8      locked_base_value, // between 0 and 31
		     UWORD8      current_entry,     // between base_value and 31
		     PRESERVED_t p_bit)
{
UWORD16 VA_tag_I2, VA_tag_I1;
  VA_tag_I1 = ((virtual_address & 0xFFF00000) >> 20);
  VA_tag_I2 = ((virtual_address & 0x000FFC00) >> 10);

    switch(mmu_name) 
    { 
    case HSAB_MMU : 
      { 
       // Write CAM msb and lsb into CAM_REG_H and CAM_REG_L registers
       HSABMMU_CAM_H_REG = (VA_tag_I1 >> 2); 
       HSABMMU_CAM_L_REG = (slst_bit | (p_bit << 3) | (VA_tag_I2 << 4) | \
                         ((VA_tag_I1 & 0x0003) << 14) ); 
			 
       // Write RAM msb and lsb into RAM_REG_H and RAM_REG_L registers
       HSABMMU_RAM_H_REG = (physical_address >> 16); \
       HSABMMU_RAM_L_REG = ((ap_bits << 8) | (physical_address & 0x0000FC00)); 
       HSABMMU_LOCK_REG = ((current_entry << 4) | (locked_base_value << 10));      
       // write 1 into LD_TLB_REG register
       HSABMMU_LD_TLB_REG = 1;
       break;         
      } 
    case LB_MMU : 
      { 
       // Write CAM msb and lsb into CAM_REG_H and CAM_REG_L registers
       LBMMU_CAM_H_REG = (VA_tag_I1 >> 2); 
       LBMMU_CAM_L_REG = (slst_bit | (p_bit << 3) | (VA_tag_I2 << 4) | \
                             ((VA_tag_I1 & 0x0003) << 14) ); 
			     		 
       // Write RAM msb and lsb into RAM_REG_H and RAM_REG_L registers
       LBMMU_RAM_H_REG = (physical_address >> 16); 
       LBMMU_RAM_L_REG = ((ap_bits << 8) | (physical_address & 0x0000FC00)); 
       LBMMU_LOCK_REG = ((current_entry << 4) | (locked_base_value << 10));   
       // write 1 into LD_TLB_REG register
       LBMMU_LD_TLB_REG = 1;  
       break;         
      } 
    case DSP_MMU : 
      { 
       // Write CAM msb and lsb into CAM_REG_H and CAM_REG_L registers
       DSPMMU_CAM_H_REG = (VA_tag_I1 >> 2); 
       DSPMMU_CAM_L_REG = (slst_bit | (p_bit << 3) | (VA_tag_I2 << 4) | \
                         ((VA_tag_I1 & 0x0003) << 14) ); 	
			 	 
       // Write RAM msb and lsb into RAM_REG_H and RAM_REG_L registers
       DSPMMU_RAM_H_REG = (physical_address >> 16); 
       DSPMMU_RAM_L_REG = ((ap_bits << 8) | (physical_address & 0x0000FC00)); 
       DSPMMU_LOCK_REG = ((current_entry << 4) | (locked_base_value << 10));
       // write 1 into LD_TLB_REG register
       DSPMMU_LD_TLB_REG = 1;        
       break;         
      } 
    } 
}