omap30_system_init.c

有关于USB的一些主机端驱动

//-------------------------------------------------------------------------------
//          TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION  
//   Property of Texas Instruments
//   For Unrestricted Internal Use Only
//   Unauthorized reprofuction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work
//   Created 2000,  (C) Copyright 2000 Texas Instruments. All rights reserved
//
//-------------------------------------------------------------------------------
 
#include "omap30.h"
#include "FPGA_peripherals.h"
#include "armperipherals.h"

//-------------------------------------------------------------------------------
//
//  GLOBAL DEFINITIONS
//
//-------------------------------------------------------------------------------

//Watch dog timer register all are 16bits
#define WatchDogTimerBase 0xfffec800
#define WatchDogTimerControl WatchDogTimerBase  //reset value = 0x02;  //R/W
#define WatchDogLoadTimer WatchDogTimerBase+0x02
#define WatchDogReadTimer WatchDogTimerBase+0x04
#define WatchDogTimerMode WatchDogTimerBase+0x08               //R/W

void BOOT_SystemInit ( void )
{
   int i;
   struct MPU_CLK_reset_power_CTL_struct * pMPU_CRPC \
	= (struct MPU_CLK_reset_power_CTL_struct*)0xfffece00;
   struct FPGA_internal_register_set_struct* pFPGA_IRS \
 	= (struct FPGA_internal_register_set_struct*)0x08000000; 
   MultiplexPinControl *FUNC_MUX_CTRL_0=(MultiplexPinControl*)0xFFFE1000;
   struct MPU_TIPB_struct //*pMPU_TIPB1 = (struct MPU_TIPB_struct*)0xFFFECA00,
				*pMPU_TIPB2 = (struct MPU_TIPB_struct*)0xFFFED300;

// Disable WatchDog Timer
   *(volatile UWORD32 *) 0xFFFEC808 = 0xF5;
   *(volatile UWORD32 *) 0xFFFEC808 = 0xA0;
  
// Set clocking scheme to sync scalable
  CLKRST_SetClockMode(SCAL_MODE_CK);

// Enable peripheral clocks  
// CLKRST_SetPeripheralClockEnable(ALL_CK,ENABLE);   
(*(int *)(0xfffece00)) |= 0x0506;
// Use ARM clock and not TC clock for interrupt handler  
  /*SetGroupBits(CLKRST_ARM_CKCTL,CLKRST_ARM_CKCTL_ARM_INTHCK_POS,CLKRST_ARM_CKCTL_ARM_INTHCK_NUMB,0x1);*/

// Set common frequency
/* Set DPLL 120MHz... */  
  /*BOOT_SetClockDomain();*/

  CLKRST_DpllSetClockandLock(20, DPLL_COMMON_DIVIDER, DPLL1);

/* Wait DPLL to lock *///
  while( !GetGroupBits(DPLL_DPLL1_CTL_REG,
			DPLL_DPLL1_CTL_REG_LOCK_POS,
			DPLL_DPLL1_CTL_REG_LOCK_NUMB));            


// Branch the interrupt on the fiq
//   INT_EnableIRQ(irqStack, IRQ_STK_SIZE);            // Branch the interrupt on the fiq
   
// Release External ARM peripherals
   CLKRST_TogglePeripheralResetPin(HIGH_LEVEL);
   for(i=0;i<100;i++);

   // Disable WatchDog Timer
   *(volatile UWORD32 *) 0xFFFEC808 = 0xF5;
   *(volatile UWORD32 *) 0xFFFEC808 = 0xA0;


	/* Hardware setup first.  Pin muliplexing. */
	*FUNC_MUX_CTRL_0 |= 1<<25; /* Enable the gating of the UART1 rx and tx pins. */
	*FUNC_MUX_CTRL_0 &= ~(0x3<<16);
	*FUNC_MUX_CTRL_0 |= 0x2<<16; /* uwire_sdo <= DTR of UART1. */


	/* FPGA line driver switch.  NB: SHDN_UART2_B = 5 in OMAP Innovator */
	pFPGA_IRS->power_CTL |= 0x60; 
	for(i=0;i<30000;i++);

	/* enable PERP clock */
	pMPU_CRPC->arm_idlect2 |= 1<<1;
	pMPU_CRPC->arm_idlect2 |= 1<<2;
	
	/* Continue the TIPB bridge stuff from here. */
	/* UART1 is on strobe 0 of the public peripheral bridge. */
	pMPU_TIPB2->TIPB_CNTL &= 0xfff0; 
	pMPU_TIPB2->TIPB_CNTL |= 0x0002; /* Division factor for strobe 0. */

   
}

//-------------------------------------------------------------------------------
// NAME        : BOOT_DSP 
// DESCRIPTION : Release DSP Reset 
// PARAMETERS  : None
// RETURN VALUE: None 
// LIMITATIONS : None                                  
//-------------------------------------------------------------------------------
void BOOT_DSP (void)
{
  // Enable DSP Clock
  CLKRST_EnableDisableDspClock(ENABLE);

  // Enable API Interface Clock
  CLKRST_SetPeripheralClockEnable(API_CK, ENABLE);

  // Set the API interface
  APIF_CtrlSetup(API_HIGH_FREQ_HIGH, API_TIMEOUT_EN, API_API_ERR_EN, 
                API_ACCESS_FACTOR_1, API_TIMEOUT_MAX, API_ENDIANISM_NO_CONVERT, 
                API_ACCESS_PRIORITY_ARM_DMA_HSAB);

  // Tell the DSP to boot internaly
  APIF_DSPBootConfig(API_DSP_BOOT_INTERNAL);
//  APIF_DSPBootConfig(API_DSP_BOOT_EMIF16);

  // Release MCUReset (to release API, EMIF and Rhea).
  CLKRST_DriveInterfaceDspReset(HIGH_LEVEL);

  // DSP reset
  CLKRST_DriveDspReset(HIGH_LEVEL);
}