omap30_clkrst.c

有关于USB的一些主机端驱动

//-------------------------------------------------------------------------------
//          TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION  
//   Property of Texas Instruments
//   For Unrestricted Internal Use Only
//   Unauthorized reprofuction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work
//   Created 2000,  (C) Copyright 2000 Texas Instruments. All rights reserved
//
//------------------------------------------------------------------------------
#include "omap30.h"
#define TIMEOUT_LOCK    31000

//-------------------------------------------------------------------------------
//
//  FUNCTIONS
//
//-------------------------------------------------------------------------------

//-------------------------------------------------------------------------------
// NAME        : CLKRST_DpllSetClockandLock
// DESCRIPTION : Modify the value output from dpll
// PARAMETERS  : multiplier       a value which belong  : 1-31
//               
//               divider          a value which belong  : 1-4
// RETURN VALUE: IS_OK if correct NOT_OK if not
// LIMITATIONS : None
//-------------------------------------------------------------------------------
BOOL CLKRST_DpllSetClockandLock( UWORD8 multiplier , UWORD8 divider, DPLLTYPE_t  dpllreglabel)
{
  UWORD32 i=0;
  UWORD16 temp=0;

 if ((divider<1) OR (divider>4))
     return(NOT_OK);


 if ((multiplier<1) OR (multiplier>31))
     return(NOT_OK);

 //Correct the value to set in the register
 divider--; 

   switch(dpllreglabel)
      {
      case DPLL1 :
         {
         if ((multiplier != 0) AND (multiplier != 1))
            {
            SetGroupBits16(DPLL_DPLL1_CTL_REG,DPLL_DPLL1_CTL_REG_PLL_MULT_POS,DPLL_DPLL1_CTL_REG_PLL_MULT_NUMB,multiplier);
            SetGroupBits16(DPLL_DPLL1_CTL_REG,DPLL_DPLL1_CTL_REG_PLL_DIV_POS,DPLL_DPLL1_CTL_REG_PLL_DIV_NUMB,divider);
            SetGroupBits16(DPLL_DPLL1_CTL_REG,DPLL_DPLL1_CTL_REG_PLL_ENABLE_POS,DPLL_DPLL1_CTL_REG_PLL_ENABLE_NUMB,ENABLE);
            do
             {
              i++;
              }
            while( (!GetGroupBits(DPLL_DPLL1_CTL_REG,DPLL_DPLL1_CTL_REG_LOCK_POS,DPLL_DPLL1_CTL_REG_LOCK_NUMB)) AND (i<TIMEOUT_LOCK));
            }
         else
             {
             SetGroupBits16(DPLL_DPLL1_CTL_REG,DPLL_DPLL1_CTL_REG_PLL_ENABLE_POS,DPLL_DPLL1_CTL_REG_PLL_ENABLE_NUMB,DISABLE);
             SetGroupBits16(DPLL_DPLL1_CTL_REG,DPLL_DPLL1_CTL_REG_BYPASS_DIV_POS,DPLL_DPLL1_CTL_REG_BYPASS_DIV_NUMB,divider);
             }
          break;
         }

      case DPLL2 :
         {
         if ((multiplier != 0) AND (multiplier != 1))
            {
            SetGroupBits16(DPLL_DPLL2_CTL_REG,DPLL_DPLL2_CTL_REG_PLL_MULT_POS,DPLL_DPLL2_CTL_REG_PLL_MULT_NUMB,multiplier);
            SetGroupBits16(DPLL_DPLL2_CTL_REG,DPLL_DPLL2_CTL_REG_PLL_DIV_POS,DPLL_DPLL2_CTL_REG_PLL_MULT_NUMB,divider);
            SetGroupBits16(DPLL_DPLL2_CTL_REG,DPLL_DPLL2_CTL_REG_PLL_ENABLE_POS,DPLL_DPLL2_CTL_REG_PLL_ENABLE_NUMB,ENABLE);
            do
             {
              i++;
              }
            while( (!GetGroupBits(DPLL_DPLL2_CTL_REG,DPLL_DPLL2_CTL_REG_LOCK_POS,DPLL_DPLL2_CTL_REG_LOCK_NUMB)) AND (i<TIMEOUT_LOCK));
            }
         else
             {
             SetGroupBits16(DPLL_DPLL2_CTL_REG,DPLL_DPLL2_CTL_REG_PLL_ENABLE_POS,DPLL_DPLL2_CTL_REG_PLL_ENABLE_NUMB,DISABLE);
             SetGroupBits16(DPLL_DPLL2_CTL_REG,DPLL_DPLL2_CTL_REG_BYPASS_DIV_POS,DPLL_DPLL2_CTL_REG_BYPASS_DIV_NUMB,divider);
             }
          break;
         }

      case DPLL3 :
         {
         if ((multiplier != 0) AND (multiplier != 3))
            {
            SetGroupBits16(DPLL_DPLL3_CTL_REG,DPLL_DPLL3_CTL_REG_PLL_MULT_POS,DPLL_DPLL3_CTL_REG_PLL_MULT_NUMB,multiplier);
            SetGroupBits16(DPLL_DPLL3_CTL_REG,DPLL_DPLL3_CTL_REG_PLL_DIV_POS,DPLL_DPLL3_CTL_REG_PLL_MULT_NUMB,divider);
            SetGroupBits16(DPLL_DPLL3_CTL_REG,DPLL_DPLL3_CTL_REG_PLL_ENABLE_POS,DPLL_DPLL3_CTL_REG_PLL_ENABLE_NUMB,ENABLE);
            do
             {
              i++;
              }
            while( (!GetGroupBits(DPLL_DPLL3_CTL_REG,DPLL_DPLL3_CTL_REG_LOCK_POS,DPLL_DPLL3_CTL_REG_LOCK_NUMB)) AND (i<TIMEOUT_LOCK));
            }
         else
             {
             SetGroupBits16(DPLL_DPLL3_CTL_REG,DPLL_DPLL3_CTL_REG_PLL_ENABLE_POS,DPLL_DPLL3_CTL_REG_PLL_ENABLE_NUMB,DISABLE);
             SetGroupBits16(DPLL_DPLL3_CTL_REG,DPLL_DPLL3_CTL_REG_BYPASS_DIV_POS,DPLL_DPLL3_CTL_REG_BYPASS_DIV_NUMB,divider);
             }
          break;
         }

     default :
         {
	 return(NOT_OK);
         break;
         }
    }//end switch

  if (i>TIMEOUT_LOCK)
    return(NOT_OK);
  else
    return(IS_OK);

    
} 

//-------------------------------------------------------------------------------
// NAME        : CLKRST_SetPeripheralClockEnable 
// DESCRIPTION : Enable/Disable the selected peripheral clock
// PARAMETERS  : PerifName
//                         WDGTIM_CK,   
//                         XORPC_CK,    
//                         PER_CK,      
//                         LCD_CK,      
//                         LB_CK,       
//                         HSAB_CK,     
//                         API_CK,      
//                         TIM_CK,      
//                         DMA_REQ_CK,  
//                         GPIO_CK,     
//                         LBFREE_CK,   
//                         ALL_CK        
//                and State=ENABLE or DISABLE
// RETURN VALUE: IS_OK if the operation succeed
//               NOT_OK if not      
//  LIMITATIONS : None                                      
//-------------------------------------------------------------------------------
BOOL CLKRST_SetPeripheralClockEnable(CLOCK_SWITCH_t PerifName, BOOL State)
{
UWORD16 Pos, Numb;

switch (PerifName)
  {
  case WDGTIM_CK ://watchdog timer clock
    {
    Pos=CLKRST_ARM_IDLECT2_EN_WDTCK_POS;
    Numb=CLKRST_ARM_IDLECT2_EN_WDTCK_NUMB;
    break;
    }

  case XORPC_CK ://vtcxo reference peripheral
    {
    Pos=CLKRST_ARM_IDLECT2_EN_XORPCK_POS;
    Numb=CLKRST_ARM_IDLECT2_EN_XORPCK_NUMB;
    break;
    }

  case PER_CK ://external peripheral
    {
    Pos=CLKRST_ARM_IDLECT2_EN_PERCK_POS;
    Numb=CLKRST_ARM_IDLECT2_EN_PERCK_NUMB;
    break;
    }

  case LCD_CK ://lcd 
    {
    Pos=CLKRST_ARM_IDLECT2_EN_LCDCK_POS;
    Numb=CLKRST_ARM_IDLECT2_EN_LCDCK_NUMB;
    break;
    }

  case LB_CK ://LB  clock
    {
    Pos=CLKRST_ARM_IDLECT2_EN_LBCK_POS;
    Numb=CLKRST_ARM_IDLECT2_EN_LBCK_NUMB;
    break;
    }

  case HSAB_CK ://HSAB  clock
    {
    Pos=CLKRST_ARM_IDLECT2_EN_HSABCK_POS;
    Numb=CLKRST_ARM_IDLECT2_EN_HSABCK_NUMB;
    break;
    }


  case API_CK ://API  clock
    {
    Pos=CLKRST_ARM_IDLECT2_EN_APICK_POS;
    Numb=CLKRST_ARM_IDLECT2_EN_APICK_NUMB;
    break;
    }

  case TIM_CK ://os timer
    {
    Pos=CLKRST_ARM_IDLECT2_EN_TIMCK_POS;
    Numb=CLKRST_ARM_IDLECT2_EN_TIMCK_NUMB;
    break;
    }

  case DMA_REQ_CK ://DMA clock
    {
    Pos=CLKRST_ARM_IDLECT2_DMACK_REQ_POS;
    Numb=CLKRST_ARM_IDLECT2_DMACK_REQ_NUMB;
    break;
    }

  case GPIO_CK ://GPIO clock
    {
    Pos=CLKRST_ARM_IDLECT2_EN_GPIOCK_POS;
    Numb=CLKRST_ARM_IDLECT2_EN_GPIOCK_NUMB;
    break;
    }

  case LBFREE_CK ://LBFREE clock
    {
    Pos=CLKRST_ARM_IDLECT2_EN_LBFREECK_POS;
    Numb=CLKRST_ARM_IDLECT2_EN_LBFREECK_NUMB;
    break;
    }

  case ALL_CK ://ALL clocks
    {
    if (State==ENABLE)
        {
        SetGroupBits16(CLKRST_ARM_IDLECT2,0,11,0xFFFF);
        }
    else
        {
        SetGroupBits16(CLKRST_ARM_IDLECT2,0,11,0x0);
        }

    return(TRUE);
    }

  default :
    {
    return(FALSE);
    }
  }

  SetGroupBits16(CLKRST_ARM_IDLECT2,Pos,Numb,State);
  return(TRUE);

}

//-------------------------------------------------------------------------------
// NAME        : CLKRST_SetDspPeripheralClockEnable 
// DESCRIPTION : Enable/Disable the selected peripheral clock
// PARAMETERS  : PerifName
//                        DSP_WDGTIM_CK   
//                        DSP_XORPC_CK    
//                        DSP_PER_CK      
//                        DSP_UART_CK     
//                        DSP_GPIO_CK     
//                        DSP_TIM_CK      
//                        DSP_ALL_CK       
//                and State=ENABLE or DISABLE
// RETURN VALUE: IS_OK if the operation succeed
//               NOT_OK if not      
//-------------------------------------------------------------------------------
BOOL CLKRST_SetDspPeripheralClockEnable(DSP_CLOCK_SWITCH_t PerifName, BOOL State)
{
UWORD16 Pos, Numb;

switch (PerifName)
  {
  case DSP_WDGTIM_CK ://watchdog timer clock
    {
    Pos=DSPCLKM_DSP_IDLECT2_EN_WDTCK_POS;
    Numb=DSPCLKM_DSP_IDLECT2_EN_WDTCK_NUMB;
    break;
    }

  case DSP_XORPC_CK ://vtcxo reference peripheral
    {
    Pos=DSPCLKM_DSP_IDLECT2_EN_XORPCK_POS;
    Numb=DSPCLKM_DSP_IDLECT2_EN_XORPCK_NUMB;
    break;
    }

  case DSP_PER_CK ://external peripheral
    {
    Pos=DSPCLKM_DSP_IDLECT2_EN_PERCK_POS;
    Numb=DSPCLKM_DSP_IDLECT2_EN_PERCK_NUMB;
    break;
    }

  case DSP_UART_CK ://uart 
    {
    Pos=DSPCLKM_DSP_IDLECT2_EN_UARTCK_POS;
    Numb=DSPCLKM_DSP_IDLECT2_EN_UARTCK_NUMB;
    break;
    }

  case DSP_GPIO_CK ://GPIO clock
    {
    Pos=DSPCLKM_DSP_IDLECT2_EN_GPIOCK_POS;
    Numb=DSPCLKM_DSP_IDLECT2_EN_GPIOCK_NUMB;
    break;
    }

  case DSP_TIM_CK ://os timer
    {
    Pos=DSPCLKM_DSP_IDLECT2_EN_TIMCK_POS;
    Numb=DSPCLKM_DSP_IDLECT2_EN_TIMCK_NUMB;
    break;
    }

  case DSP_ALL_CK ://ALL clocks
    {
        if (State==ENABLE)
            {
            SetGroupBits16(DSPCLKM_DSP_IDLECT2,0,11,0xFFFF);
            }
        else
            {
            SetGroupBits16(DSPCLKM_DSP_IDLECT2,0,11,0x0);
            }

    return(TRUE);
    }

  default :
    {
    return(FALSE);
    }
  }

  SetGroupBits16(DSPCLKM_DSP_IDLECT2,Pos,Numb,State);
  return(TRUE);

}