syscalls.c

有关于USB的一些主机端驱动

/* Setup a interrupt source for one of the interrupt handlers each of which has 32
 *   interrupt sources. Because the first and second source of handler 1 are hardwired to 
 *    the IRQ and FIQ outputs of handler 2, there are only 62 left for peripherals' use.
 *    SourceNO from 0 to 31 corresponds to handler 2's source from 0 to 31;
 *    SourceNO from 32 to 61 corresponds to handler 1's source from 2 to 31; */
#include "..\header\armperipherals.h"
#include "..\header\FPGA_peripherals.h"


/* OK, OMAP1510 has only two interrupt handlers, each of which has 32 interrupt sources, 
  * each of which can be of edge triggered or level triggered, of priority from 0 - 31, 
  * be routed to FIQ or IRQ of its handler.  */

/*
int SetupINTSourceHandler( unsigned int SourceNO,
			    unsigned int TriggerType,
			     unsigned int Priority,
			      unsigned int IRQorFIQ ) {
	unsigned int handlerNO;							   
	struct interrupt_handler_struct *pINTHandler[2] = {(struct interrupt_handler_struct*)0xFFFECB00,
			(struct interrupt_handler_struct*)0xFFFE0000};
	
	if (SourceNO> 63
		|| TriggerType > 1
		  || Priority > 31
	            || IRQorFIQ > 1 ) {
		printf("Setup INTH failed.SourceNO: %d TriggerType: %d Priority: %d IRQorFIQ: %d\n ",SourceNO, TriggerType, Priority, IRQorFIQ); 
		return -1;       
	}
	if (SourceNO > 31) {
  		handlerNO = 0;
		SourceNO -= 32;
	}
	else 
		handlerNO = 1;	
    // Mask the interrupt first to avoid confusion 
	pINTHandler[handlerNO]->MIR |= 1<<SourceNO;
	//pINTHandler[handlerNO]->MIR = 0xffffffff;
	
	// Set the interrupt level register 
	pINTHandler[handlerNO]->ILR[SourceNO] = Priority<<PRIORITY|TriggerType<<TRIGGER_TYPE|IRQorFIQ<<TRIGGER_ROUTE;	                                              
	                                              
	// Clear the ITR bit and unmask the source. /
	//pINTHandler[handlerNO]->ITR &= ~(1<<SourceNO); 
	pINTHandler[handlerNO]->ITR |= 1<<SourceNO; 	
	//temp = pINTHandler[handlerNO]->ITR;          
	//temp &= ~(1<<SourceNO);
	pINTHandler[handlerNO]->MIR &= ~(1<<SourceNO);
	
	//New IRQ or FIQ agreement 
	//pINTHandler[handlerNO]->CONTROL_REG |= (IRQorFIQ == 0)?2:1;

	return 0;	
} */	
/* To generate timer interrupts. 
 * timerNO is the number of the selected timer;
 * LoadTime is the value to be loaded into the LOAD register;
 * OneShot_CLKSRC, the 16th bit of which determines whether the interrupt generation
 * 	is one shot or continuous and the first bit of which determines whether the clock 
 * 	source of the timers is CK_GEN1 or CLK1. 
 */
int SetupTimerHandler( unsigned int timerNO, unsigned int LoadTime, unsigned int OneShot_CLKSRC,\
		    		unsigned int Prescaler ) {
	struct timer_CTL_struct *pTimer[3] = {(struct timer_CTL_struct*)0xFFFEC500,
			(struct timer_CTL_struct*)0xFFFEC600,
				(struct timer_CTL_struct*)0xFFFEC700};
	struct MPU_CLK_reset_power_CTL_struct * pMPU_CRPC \
				= (struct MPU_CLK_reset_power_CTL_struct*)0xfffece00;

	if (timerNO > 2 || Prescaler > 7) {
		return -1;
	}

	pTimer[timerNO]->CNTL_TIMER &= ~(1<<STARTCLOCK); /* Stop the clock first. */
	if ( LoadTime == 0 ) /* Shutdown the timer. */
		return 0;
	if ( OneShot_CLKSRC & 0x00000001 )
		pMPU_CRPC->arm_ckctl |= 1<<ARM_TIMXO; /* Select CK_GEN1 as the timer clock. */	
	else
		pMPU_CRPC->arm_ckctl &= ~(1<<ARM_TIMXO); /* Select CLKIN as the timer clock. */	

	pMPU_CRPC->arm_idlect2 |= 1<<EN_TIMCK; /* Supply the clock to timer modules. */
	pTimer[timerNO]->LOAD_TIM = LoadTime;
	pTimer[timerNO]->CNTL_TIMER = 1<<FREECLOCK|Prescaler<<TIMERPRESCALER\
			|1<<CLOCK_ENABLE|(((OneShot_CLKSRC&0x00010000)>>16)^0x1)<<AUTORELOAD;
	
	pTimer[timerNO]->CNTL_TIMER |= 1<<STARTCLOCK;

	return 0;
}


/* a0: 1:0 --  Enable/Disable ARM9TDMI to be interrupted by IRQ.  */
 unsigned int SetIRQHandler( unsigned int a0 ) {
	if ( a0 != 0 ) {
		asm("\tmrs r0, spsr");
		asm("\tbic r0, r0, #0x80"); // Enable IRQ for ARM925T
	} else {
		asm("\tmrs r0, spsr");	
		asm("\torr r0, r0, #0x80"); 
    }
	asm("\tmsr spsr, r0");   

	return 0;
 }