usb-ohci.c

有关于USB的一些主机端驱动

/*
 * URB OHCI HCD (Host Controller Driver) for USB.
 *
 * (C) Copyright 1999 Roman Weissgaerber <[e-mail]>
 * (C) Copyright 2000-2001 David Brownell <[e-mail]>
 * 
 * [ Initialisation is based on Linus'  ]
 * [ uhci code and gregs ohci fragments ]
 * [ (C) Copyright 1999 Linus Torvalds  ]
 * [ (C) Copyright 1999 Gregory P. Smith]
 * 
 * 
 * History:
 * 
 * 2001/09/19 USB_ZERO_PACKET support (Jean Tourrilhes)
 * 2001/07/17 power management and pmac cleanup (Benjamin Herrenschmidt)
 * 2001/03/24 td/ed hashing to remove bus_to_virt (Steve Longerbeam);
 	pci_map_single (db)
 * 2001/03/21 td and dev/ed allocation uses new pci_pool API (db)
 * 2001/03/07 hcca allocation uses pci_alloc_consistent (Steve Longerbeam)
 *
 * 2000/09/26 fixed races in removing the private portion of the urb
 * 2000/09/07 disable bulk and control lists when unlinking the last
 *	endpoint descriptor in order to avoid unrecoverable errors on
 *	the Lucent chips. (rwc@sgi)
 * 2000/08/29 use bandwidth claiming hooks (thanks Randy!), fix some
 *	urb unlink probs, indentation fixes
 * 2000/08/11 various oops fixes mostly affecting iso and cleanup from
 *	device unplugs.
 * 2000/06/28 use PCI hotplug framework, for better power management
 *	and for Cardbus support (David Brownell)
 * 2000/earlier:  fixes for NEC/Lucent chips; suspend/resume handling
 *	when the controller loses power; handle UE; cleanup; ...
 *
 * v5.2 1999/12/07 URB 3rd preview, 
 * v5.1 1999/11/30 URB 2nd preview, cpia, (usb-scsi)
 * v5.0 1999/11/22 URB Technical preview, Paul Mackerras powerbook susp/resume 
 * 	i386: HUB, Keyboard, Mouse, Printer 
 *
 * v4.3 1999/10/27 multiple HCs, bulk_request
 * v4.2 1999/09/05 ISO API alpha, new dev alloc, neg Error-codes
 * v4.1 1999/08/27 Randy Dunlap's - ISO API first impl.
 * v4.0 1999/08/18 
 * v3.0 1999/06/25 
 * v2.1 1999/05/09  code clean up
 * v2.0 1999/05/04 
 * v1.0 1999/04/27 initial release
 */
 /*
#include <linux/config.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/smp_lock.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/timer.h>
#include <linux/list.h>
#include <linux/interrupt.h>  // for in_interrupt() 
#undef DEBUG
#include <linux/usb.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/unaligned.h>
*/
#define OHCI_USE_NPS		// force NoPowerSwitching mode
// #define OHCI_VERBOSE_DEBUG	/* not always helpful */

#include "usb-ohci.h"
//#include "omap-usb-ohci.h"
/*
#ifdef CONFIG_PMAC_PBOOK
#include <asm/feature.h>
#include <asm/pci-bridge.h>
#ifndef CONFIG_PM
#define CONFIG_PM
#endif
#endif
*/
/*
 * Version Information
 */
#define DRIVER_VERSION "v5.3"
#define DRIVER_AUTHOR "Roman Weissgaerber <[e-mail]>, David Brownell"
#define DRIVER_DESC "USB OHCI Host Controller Driver"
extern void list_add(struct list_head *new, struct list_head *head);
extern void * hub_probe(struct usb_device *dev, unsigned int i);

static LIST_HEAD (ohci_hcd_list);
struct omap_dev omap_hc_dev;

extern int list_empty(struct list_head *head);
extern void list_del_init(struct list_head *entry);
extern void atomic_dec(atomic_t *v);
//extern static void usb_api_blocking_completion(urb_t *urb);

/* For initializing controller (mask in an HCFS mode too) */
#define	OHCI_CONTROL_INIT \
	(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE

#define OHCI_UNLINK_TIMEOUT	(HZ / 10)

//static spinlock_t usb_ed_lock = SPIN_LOCK_UNLOCKED;

void omap_free_consistent(size_t size, void *vaddr)
{
	free((struct ohci_hcca *)vaddr);
}

unsigned long mpuva_to_lbva(void *mpuva){
	unsigned long tmp_value;

	if(mpuva){
//		tmp_value = virt_to_phys(mpuva);
		tmp_value =(unsigned int)mpuva+ 0x20000000;
	}
	else
		tmp_value =0x00000000;

//	printf("Local Bus address: %X\n",tmp_value);
	return tmp_value;
}

void * lbva_to_mpuva(unsigned long lbva){
	void * tmp_value;

	if(lbva){
		tmp_value = (void *)(lbva-0x20000000);
	}
	else
		tmp_value =NULL;
	
	return tmp_value;
}


void *omap_alloc_consistent(size_t size,dma_addr_t *dma_handle)
{
	void *ret;
	unsigned long res;
	void *ret_tmp;
//	int gfp = GFP_ATOMIC|GFP_DMA;
	
	ret = (void *)malloc(size);
	if (ret != NULL) {
		res=0x000000ff&(unsigned long)ret;
		if(res){
			res=0x100-res;
			free(ret);
			ret_tmp=(void *)malloc(res-4);
			ret =(void *)malloc(size);
		}
		if(ret != NULL) {	
			memset(ret, 0, size);
			*dma_handle = mpuva_to_lbva(ret);
		}
	}
	return ret;
}

/* Recover a TD/ED using its collision chain */
void * dma_to_ed_td (struct hash_list_t * entry, dma_addr_t dma)
{
	struct hash_t * scan = entry->head;
	while (scan && scan->dma != dma)
		scan = scan->next;
	if (!scan);
//		BUG();
	return scan->virt;
}

struct ed *dma_to_ed (struct ohci * hc, dma_addr_t ed_dma)
{/*
	return (struct ed *) dma_to_ed_td(&(hc->ed_hash[ED_HASH_FUNC(ed_dma)]),
				      ed_dma);*/
	return (struct ed *)lbva_to_mpuva(ed_dma);
}

struct td *dma_to_td (struct ohci * hc, dma_addr_t td_dma)
{/*
	return (struct td *) dma_to_ed_td(&(hc->td_hash[TD_HASH_FUNC(td_dma)]),
				      td_dma);*/
	return (struct td *)lbva_to_mpuva(td_dma);
}

/* Add a hash entry for a TD/ED; return true on success */
int hash_add_ed_td(struct hash_list_t * entry, void * virt, dma_addr_t dma)
{
	struct hash_t * scan;
	
	scan = (struct hash_t *)malloc(sizeof(struct hash_t));
	if (!scan)
		return 0;
	
	if (!entry->tail) {
		entry->head = entry->tail = scan;
	} else {
		entry->tail->next = scan;
		entry->tail = scan;
	}
	
	scan->virt = virt;
	scan->dma = dma;
	scan->next = NULL;
	return 1;
}

int hash_add_ed (struct ohci * hc, struct ed * ed)
{
	return hash_add_ed_td (&(hc->ed_hash[ED_HASH_FUNC(ed->dma)]),
			ed, ed->dma);
}

int hash_add_td (struct ohci * hc, struct td * td)
{
	return hash_add_ed_td (&(hc->td_hash[TD_HASH_FUNC(td->td_dma)]),
			td, td->td_dma);
}


void hash_free_ed_td (struct hash_list_t * entry, void * virt)
{
	struct hash_t *scan, *prev;
	scan = prev = entry->head;

	// Find and unlink hash entry
	while (scan && scan->virt != virt) {
		prev = scan;
		scan = scan->next;
	}
	if (scan) {
		if (scan == entry->head) {
			if (entry->head == entry->tail)
				entry->head = entry->tail = NULL;
			else
				entry->head = scan->next;
		} else if (scan == entry->tail) {
			entry->tail = prev;
			prev->next = NULL;
		} else
			prev->next = scan->next;
		free(scan);
	}
}

void hash_free_ed (struct ohci * hc, struct ed * ed)
{
	hash_free_ed_td (&(hc->ed_hash[ED_HASH_FUNC(ed->dma)]), ed);
}

void hash_free_td (struct ohci * hc, struct td * td)
{
	hash_free_ed_td (&(hc->td_hash[TD_HASH_FUNC(td->td_dma)]), td);
}
/* TDs ... */
struct td *td_alloc (struct ohci *hc)
{
//	dma_addr_t	dma;
	struct td	*td;
	unsigned int res;

//	td = pci_pool_alloc (hc->td_cache, mem_flags, &dma);
	td =(struct td*)malloc(sizeof(struct td)+16);
	if (td) {
		res =(unsigned int)td & 0x0000000f;
		if(res){
			res =0x10-res;
			td =(struct td *)((unsigned int)td+res);
		}
		td->td_dma = mpuva_to_lbva((void*)td);

		/* hash it for later reverse mapping */
//		if (!hash_add_td (hc, td)) {
//			free((void *)td);
//			pci_pool_free (hc->td_cache, td, dma);
//			return NULL;
//		}
	}
	return td;
}

void td_free (struct ohci *hc, struct td *td)
{
//	hash_free_td (hc, td);
	free((void *)td);
//	pci_pool_free (hc->td_cache, td, td->td_dma);
}

void * allocat_ohci_mem(size_t size){
	void *ret,*ret_tmp;
	unsigned int res;

	ret=(void *)malloc(size+16);
	if(ret){
		res=(unsigned int)ret & 0x0000000f;
		if(res){
			res=0x10-res;
			ret=(void *)((unsigned int)ret+res);			
		}
	}
	return ret;
}

/* DEV + EDs ... only the EDs need to be consistent */
struct ohci_device *ohci_dev_alloc (struct ohci *hc)
{
	dma_addr_t		dma;
	struct ohci_device	*dev;
	int			i, offset;

//	dev = (struct ohci_device *)malloc(sizeof(*dev));
	dev = (struct ohci_device *)allocat_ohci_mem(sizeof(*dev));
	printf("ED start address:0x%X\n",(unsigned int)dev);
	if (dev) {
//		printf("sizeof(*dev)[struct ohci_device * dev] is:%d\n",sizeof(*dev));
		memset (dev, 0, sizeof (*dev));
		dev->dma = dma=mpuva_to_lbva((void *) dev);
		offset = ((char *)&dev->ed) - ((char *)dev);
		for (i = 0; i < NUM_EDS; i++, offset += sizeof(dev->ed [0]))
			dev->ed [i].dma = dma + offset;
		/* add to hashtable if used */
	}
	return dev;
}

void dev_free (struct ohci *hc, struct ohci_device *dev)
{
	free (dev);
}


void hc_register_info(ohci_t *ohci){
	unsigned int val_tmp;

	val_tmp =readl(&ohci->regs->revision);
	printf("Revision:\t0x%X\n",val_tmp);
	val_tmp =readl(&ohci->regs->control);
	printf("Control register:\t0x%X\n",val_tmp);
	val_tmp =readl(&ohci->regs->cmdstatus);
	printf("CmdStatus register:\t0x%X\n",val_tmp);
	val_tmp =readl(&ohci->regs->intrstatus);
	printf("InterruptStatus register:\t0x%X\n",val_tmp);
	val_tmp =readl(&ohci->regs->intrenable);
	printf("InterruptEnable register:\t0x%X\n",val_tmp);
	
	val_tmp =readl(&ohci->regs->hcca);
	printf("HCCA register:\t0x%X\n",val_tmp);
	val_tmp =readl(&ohci->regs->ed_periodcurrent);
	printf("ED Periodcurretn register:\t0x%X\n",val_tmp);
	val_tmp =readl(&ohci->regs->ed_controlhead);
	printf("ED ControlHead register:\t0x%X\n",val_tmp);
	val_tmp =readl(&ohci->regs->ed_controlcurrent);
	printf("ED ControlCurrent register:\t0x%X\n",val_tmp);
	val_tmp =readl(&ohci->regs->ed_bulkhead);
	printf("ED BulkHead register:\t0x%X\n",val_tmp);
	val_tmp =readl(&ohci->regs->ed_bulkcurrent);
	printf("ED BulkCurrent register:\t0x%X\n",val_tmp);
	val_tmp =readl(&ohci->regs->donehead);
	printf("DoneHead register:\t0x%X\n",val_tmp);
	val_tmp =readl(&ohci->regs->periodicstart);
	printf("HCPeriodicStart register:\t0x%X\n",val_tmp);
	val_tmp =readl(&ohci->regs->lsthresh);
	printf("LSThreshold register:\t0x%X\n",val_tmp);
	
	val_tmp =readl(&ohci->regs->roothub.a);
	printf("Root hub Descriptor A:\t0x%X\n",val_tmp);
	val_tmp =readl(&ohci->regs->roothub.b);
	printf("Root hub Descriptor B:\t0x%X\n",val_tmp);
	val_tmp =readl(&ohci->regs->roothub.status);
	printf("Root hub Status:\t0x%X\n",val_tmp);
	val_tmp =readl(&ohci->regs->roothub.portstatus[0]);
	printf("USBH(port 1) PortStatus:\t0x%X\n",val_tmp);
	val_tmp =readl(&ohci->regs->roothub.portstatus[1]);
	printf("USB1(port 2) PortStatus:\t0x%X\n",val_tmp);
	val_tmp =readl(&ohci->regs->roothub.portstatus[2]);
	printf("USB2(port 3) PortStatus:\t0x%X\n",val_tmp);


	printf("PLL_CTRL:\t0x%X\n",readw(0xFFFECF00));//0xFFFECF00:PLL_CTRL
	printf("Arm CKCTL:\t0x%X\n",readw(0xFFFECE00));//0xFFFECE00:ARM_CKCTL
	printf("ARM_IDLECT1:\t0x%X\n",readw(0xfffece04));//0xfffece04:ARM_IDLECT1
	printf("ARM_SYSST:\t0x%X\n",readw(0xFFFECE18));//0xFFFECE18:ARM_SYSST
	printf("ARM_RSTCT2:\t0x%X\n",readw(0xFFFECE14));//0xFFFECE14:ARM_RSTCT2
	printf("APLL_CTRL_REG:\t0x%X\n",readw(0xfffe084c));//0xfffe084c:APLL_CTRL_REG
	printf("DPLL_CTRL_REG:\t0x%X\n",readw(0xfffe083c));//0xfffe083c:DPLL_CTRL_REG
	printf("SOFT_REQ_REG:\t0x%X\n",readw(0xfffe0834));//0xfffe0834:SOFT_REQ_REG
	printf("CLOCK_CTRL_REG:\t0x%X\n",readw(0xfffe0830));//0xfffe0830:CLOCK_CTRL_REG
	printf("MOD_CONF_CTRL_0:\t0x%X\n",readl(0xfffe1080));//0xfffe1080:MOD_CONF_CTRL_0
	printf("LB_CLOCK_DIV:\t0x%X\n",readl(0xfffec10c));//0xfffec10c:LB_CLOCK_DIV
	printf("ARM_IDLECT2:\t0x%X\n",readw(0xfffece08));//0xfffece08:ARM_IDLECT2
	printf("FUNC_MUX_CTRL_0:\t0x%X\n",readl(0xfffe1000));//0xfffe1000:FUNC_MUX_CTRL_0

	printf("FUNC_MUX_CTRL_8:\t0x%X\n",readl(0xFFFE1024));//0xFFFE1024:FUNC_MUX_CTRL_8
	printf("FUNC_MUX_CTRL_9:\t0x%X\n",readl(0xFFFE1028));//0xFFFE1028:FUNC_MUX_CTRL_9
	printf("FUNC_MUX_CTRL_A:\t0x%X\n",readl(0xFFFE102C));//0xFFFE102C:FUNC_MUX_CTRL_A
	printf("FUNC_MUX_CTRL_B:\t0x%X\n",readl(0xFFFE1030));//0xFFFE1030:FUNC_MUX_CTRL_B
	printf("FUNC_MUX_CTRL_C:\t0x%X\n",readl(0xFFFE1034));//0xFFFE1034:FUNC_MUX_CTRL_C

	printf("FPGA:\t0x%X\n",readb(0x0800020c));//FPGA:0x0800020c
}



/*---------1----------------------------------------------------------------*/

/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
 * The erratum (#4) description is incorrect.  AMD's workaround waits
 * till some bits (mostly reserved) are clear; ok for all revs.
 */
 /*
u32 read_roothub(hc, register, mask) { 
	u32 temp = readl (&hc->regs->roothub.register); 
//	if (hc->flags & OHCI_QUIRK_AMD756) 	//modified by Changming HUANG
//		while (temp & mask) 
//			temp = readl (&hc->regs->roothub.register); 
	return temp; }
*/
static u32 roothub_a (struct ohci *hc)
//	{ return read_roothub (hc, a, 0xfc0fe000); }
{
	u32 temp =readl(&hc->regs->roothub.a);
	return temp;
}
static inline u32 roothub_b (struct ohci *hc)
	{ return readl (&hc->regs->roothub.b); }
static inline u32 roothub_status (struct ohci *hc)
	{ return readl (&hc->regs->roothub.status); }
static u32 roothub_portstatus (struct ohci *hc, int i)
//	{ return read_roothub (hc, portstatus [i], 0xffe0fce0); }
{
	u32 temp =readl(&hc->regs->roothub.portstatus[i]);
	return temp;
}

/*-------------------------------------------------------------------------*
 * URB support functions 
 *-------------------------------------------------------------------------*/