sst28sf040.txt

很全的flash芯片驱动程序包括：SST28SF040

	BYTE PreData;
	BYTE CurrData;
	unsigned long TimeOut = 0;

	TrueData = TrueData & 0x80;
	while ((TimeOut< 0x07FFFFFF) && (Loop))
	{
		CurrData = *Dst;
		CurrData = CurrData & 0x80;	/* mask out the DQ7 bit */
		if (TrueData == CurrData)
          Loop = FALSE;         /* ready to exit the while loop */
		TimeOut++;
	}
}


/8086 ASSEMBLY LANGUAGE DRIVERS
; ===================================================================     
; Copyright Silicon Storage Technology, Inc. (SST), 1994-1997
; EXAMPLE 8086 assembly Drivers for 28SF040 4 Mbit SuperFlash EEPROM
; Chi Chung Yin,  Silicon Storage Technology
;
; Revision 2.0, April 8, 1997
;====================================================================

ROW_SIZE	EQU	256	;Must be 256 bytes for 28SF040

SST_ID		EQU	0BFh	;SST Manufacturer抯 ID code
SST_28SF040	EQU	004h	;SST 28SF040 internal code

AUTO_PG_ERASE1	EQU	020h
AUTO_PG_ERASE2	EQU	0D0h
AUTO_PGRM	EQU	010h
RESET		EQU	0FFh
READ_ID		EQU	090h
		
ABS_SEGMENT	EQU   	0E000h



;==========================================================================
; PROCEDURE:			Check_SST_28SF040
;
; This procedure decides whether a physical hardware device has a SST抯
; 28SF040 4 Mbit SuperFlash EEPROM installed or not.
;
; Input:
;	None
;
; Output:
; 	carry bit:   SET means no SST 28SF040 installed
;	carry bit:   CLEARED means a SST 28SF040 is installed
;==========================================================================

Check_SST_28SF040	proc 	near

	push 	ax				
	push 	bx
	push	ds

	cli
	mov	ax, ABS_SEGMENT
	mov	ds, ax
	mov 	bl, ds:byte ptr [0]		; save original memory content
	mov	ds:byte ptr [0h], RESET		; reset the 28SF040 chip
	mov 	ds:byte ptr [0h], READ_ID	; issue READ_ID command to the chip
;
;Now, Check the SST 28SF040 Manufacture抯 ID and Internal Die Code
;
	mov	al, ds:byte ptr[0]
	cmp	al, SST_ID			; is this a SST part?
	jne	CSC5				; NO, then return Carry set
	mov 	al,ds:byte ptr[1]
	cmp	al, SST_28SF040			; Is it 28SF040?
	jne	CSC5				; NO, then Non-SST part
CSC4:
	mov	ds:byte ptr [0], RESET		; issure RESET command to the chip
	clc					; return with NO error
	jmp	short CSC6
CSC5:
	mov	ds:byte ptr [0], RESET		; issue RESET command to the chip
	mov	ds:byte ptr [0], bl			; restore original memory content
	stc					; return with error
CSC6:
	pop	ds
	pop	bx
	pop	ax
	
	ret
Check_SST_28SF040  endp



;=================================================================================
; PROCEDURE:			Disable_Chip_Data_Protection
;
;This procedure DISABLES the data protection feature on the 28SF040
;4 Mbit SuperFlash EEPROM.  After calling the routine, the chip can be written
;without  any additional commands.
;
; Input:
;	None
;
; Output:
;	None
;=================================================================================

Disable_Chip_Data_Protection 	proc	near

	push	ax
	push	ds

	cli
	mov	ax, ABS_SEGMENT
	mov	ds, ax

	mov 	al, byte ptr ds:[1823h]		; issue the 7-byte read sequences to the chip
	mov	al, byte ptr ds:[1820h]		; to unprotect the chip
	mov	al, byte ptr ds:[1822h]
	mov 	al, byte ptr ds:[0418h]
	mov	al, byte ptr ds:[041Bh]
	mov 	al, byte ptr ds:[0419h]
	mov	al, byte ptr ds:[041Ah]

	pop	ds
	pop	ax

	ret

Disable_Chip_Data_Protection endp



;=======================================================================================
; PROCEDURE:		 Enable_Chip_Data_Protection
;
;This procedure ENABLES the data protection feature on the 28SF040
;4 Mbit SuperFlashEEPROM.  After calling the routine, the chip cannot be written
;without disabling SDP first.  Disabling the SDP can be done by call ing the 
;"Disable_Chip_Data_Protection" routine.
;
; Input::
;	None
;
; Output:
;	None
;=======================================================================================

Enable_Chip_Data_Protection 	proc	near

	push	ax
	push	ds

	cli
	mov	ax, ABS_SEGMENT
	mov	ds, ax

	mov 	al, byte ptr ds:[1823h]		; issue the 7-byte read sequences to the chip
	mov	al, byte ptr ds:[1820h]		; to protect the chip from inadvertent program 
	mov	al, byte ptr ds:[1822h]		; operations	
	mov 	al, byte ptr ds:[0418h]
	mov	al, byte ptr ds:[041Bh]
	mov 	al, byte ptr ds:[0419h]
	mov	al, byte ptr ds:[040Ah]

	pop	ds
	pop	ax

	ret

Enable_Chip_Data_Protection endp



; =====================================================================================
; PROCEDURE:			Write_28SF040
; 
; This procedure can be used to write a total of 256 bytes at one write cycle to the 
;  28SF040 4 Mbit SuperFlash EEPROM.
;
; Input:
;	ds:si	SOURCE address containing the data which will be
;		written into the 28SF040.
;	es:di	DESTINATION address which will be written with the 
;		data passed in for ds:si
;
; Output:
;	carry bit: SET means programming error
	; 	carry bit: CLEAR means programmed O.K. 
;	SI, DI:  Contains the original values
; ======================================================================================
Write_28SF040		proc 	near
CALL    Disable_Chip_Data_Protection
	push	ax
	push	bx
	push	cx
	push	di
	push	si
	pushf			; preserve the "direction" flag in the FLAG
				; register
	cld			; clear "Direction" flag in the FLAG register
	mov	bx, di		; save DI value in BX in order to use it from programming

; =====================================================================
;				WRITE  OPERATION
;======================================================================

	mov	byte ptr es:[di], AUTO_PG_ERASE1        ; let抯 clear the page first
	mov 	byte ptr es:[di], AUTO_PG_ERASE2
	call	Check_Toggle_Ready                      ; make sure the internal hardware finish
					                ; the clear operation
	mov 	cx, ROW_SIZE		                ; check 256 bytes to make sure every byte is 0FFh
P2_0:
	mov	al, byte ptr es:[di]	                ; read back the byte just eased
	cmp	al, 0FFh			        ; is it erased?
	jnz	P2_1
	inc	di
	loop	P2_0
	jmp	short P2_3		                ; let抯 start to program the part
P2_1:	
	popf				                ; restore flag register value for stack
	stc				                ; return with error
	jmp	short P2_10
;_______________________________________________________________________________________
; 				PROGRAM operation
;_______________________________________________________________________________________
P2_3:
	mov	cx, ROW_SIZE		                ; program 256 bytes
	mov	di, bx			                ; restore original destination address (DI)
WOS1_4:
	lodsb				                ; get the byte to be written
	cmp	al, 0FFh			        ; is it 0FFh?
	jz	WOS11_5		                        ; yes, no need to program it
	push 	ax			                ; save the byte on the stack
	mov	byte ptr es:[di], AUTO_PGRM             ;  issue the AUTO_PROGRAM command
	mov	byte ptr es:[di], al	                ; program the byte
;
; Due to performance reason, we will implement "TOGGLE_BIT" test routine here.
;
	mov	al, byte ptr es:[di]	                ; read back the byte just programmed
	and 	al, 040h
Tx1:	
	mov	ah,byte ptr es:[di]	                ; read the same byte again
	and	ah, 040h
	cmp	al, ah			                ; do both reads produce the same result?
	jz	WOS1_5			                ; YES, then done because 憈oggle_bit?stops
					                ; toggling.
	xchg	ah, al			                ; NO, then keep trying until done...
	jmp 	short Tx1
WOS1_5:
	pop 	ax			                ; restore the byte just programmed
	cmp	al, byte ptr es:[di]	                ; is it the same as original?
	je	WOS11_5
	popf				                ; the byte just programmed is NOT the same as
	stc				                ; original, return error to the caller
	jmp	short P2_10		
WOS11_5:
	inc	di
	loop	WOS1_4			                ; program next byte
	
	popf
	clc				                ; clear Carry bit  to indicate NO error

P2_10:
	pop	si
	pop	di
	pop	cx
	pop	bx
	pop	ax
        pushf
        CALL    Enable_Chip_Data_Protection
        popf

	ret
Write_28SF040	endp



;====================================================================================
; PROCEDURE:			Check_Toggle_Ready
;
; During the internal write cycle, any consecutive read operation
; on DQ6 will produce alternating 0抯 and 1抯, i.e. toggling between
; 0 and 1.  When the write cycle is completed, the DQ6 data will
; stop toggling.  After the DQ6 data stops toggling, the device is ready
; for the next operation.
;
; Input:
;	es:di	must already set-up by the calller
;
; Output:
;	None
;=====================================================================================

Check_Toggle_Ready	proc	near

	push 	ax
	mov	al, es:[di]		; read a byte form the chip
	and	al,40h			; mask out the TOGGLE bit (DQ6)
CTR_Tog2:
	mov	ah,es:[di]		; read the same byte from the chip again
	and	ah, 40h			; mask out the TOGGLE BIT (DQ6)
	cmp 	al, ah			; is DQ6 still toggling?
	je	CTR_Tog3		; NO, then the programming is done
	xchg	ah, al 			; YES, then continue checking...
	jmp	short CTR_Tog2
CTR_Tog3:
	pop	ax
 	
	ret

Check_Toggle_Ready     endp



;============================================================================================
; PROCEDURE:			Check_Data_Polling
;
; During the internal write cycle, any attemp to read DQ7 of the last byte loaded during
; the page/byte-load cycle will receive the complement of the true data.  Once the 
; write cycle is completed, DQ7 will show  true data.
;
; Input:
;	es:di 	must  already set-up  by the caller
;	bl	contains the original (true) data
;
; Output: 
;	None
;=============================================================================================

Check_Data_Polling 	proc 	near

	push	ax

	and 	bl, 80h			; mask out the DQ7 bit
CDP_Tog2:
	mov	al, es:[di]		; read a byte from the chip
	and 	al,80h			; mask out the DQ7 bit
	cmp	al,bl			; is DQ7 still complementing?
	jne	CDP_Tog2		

	pop	ax

	ret

Check_Data_Polling	endp