avr2313.txt

AVR脉宽调整的程序

;---------------------------------------------------------------------------
; avr2313.inc - Include file based on 2313def.inc from Atmel, but with
;  additional comments and other handy reference material.
;                ____  ____
;       /Reset  |1   __  20| Vcc
;      rxd,pd0  |2       19| pb7,sck
;      txd,pd1  |3       18| pb6,miso
;    xtal2,out  |4       17| pb5,mosi
;     xtal1,in  |5       16| pb4
;     int0,pd2  |6       15| pb3,oc1
;     int1,pd3  |7       14| pb2
;       t0,pd4  |8       13| pb1,ain1
;       t1,pd5  |9       12| pb0,ain0
;          Gnd  |10      11| pd6,icp
;                ----------
;---------------------------------------------------------------------------

;***** Specify Device
.device AT90S2313

;***** Data Memory layout:
; 00-1FH, 32 Working registers(last 6 are XL,XH,YL,YH,ZL,ZH special)
; 20-5FH, 64 I/O registers for peripheral configuration(see below)
; 60-DFH, 128 RAM for stack and application variables
;    note register names are in decimal, so r16 is at 10H hexidecimal.

;***** Program Memory layout:
; 000-3FFH, flash memory

;***** I/O Register Definitions, $20 to $5f,
; io instructions use relative values to start of IO map in Data Memory
; see pg 60 for summary(!!!pg60, NOTE LEFT COLOUMN CONTAINS PAGE INDEXES!!!)
.equ  SREG   =$3f ; status register
.equ  SPL    =$3d ; stack pointer(this is critical!)(p13)
.equ  GIMSK  =$3b ; general interrupt mask reg
.equ  GIFR   =$3a ; general interrupt flag reg
.equ  TIMSK  =$39 ; timer Interrupt mask reg
.equ  TIFR   =$38 ; timer interrupt flag reg
.equ  MCUCR  =$35 ; MCU general control reg
.equ  MCUSR  =$34
.equ  TCCR0  =$33 ; timer0 control reg
.equ  TCNT0  =$32 ; timer0, 8-bit
.equ  TCCR1A =$2f ; timer1, control reg A
.equ  TCCR1B =$2e ; timer1, control reg B
.equ  TCNT1H =$2d ; timer1, high byte
.equ  TCNT1L =$2c ; timer1, low byte
.equ  OCR1AH =$2b ; output compare reg high byte
.equ  OCR1AL =$2a ; output compare reg low byte
.equ  ICR1H  =$25 ; timer1 input capture reg high byte
.equ  ICR1L  =$24 ; timer1 input capture reg low byte
.equ  WDTCR  =$21 ; watchdog timer control reg
.equ  EEAR   =$1e ; eeprom address reg
.equ  EEARL  =$1e ; 
.equ  EEDR   =$1d ; eeprom data reg
.equ  EECR   =$1c ; eeprom control reg
.equ  PORTB  =$18 ; port b(pb7..pb0)
.equ  DDRB   =$17 ; data direction reg, port b
.equ  PINB   =$16 ; input pins, port b
.equ  PORTD  =$12 ; data reg, port d(pd6..pd0)
.equ  DDRD   =$11 ; data direction reg, port d
.equ  PIND   =$10 ; input pins, port d
.equ  UDR    =$0c ; uart io data reg
.equ  USR    =$0b ; uart status reg
.equ  UCR    =$0a ; uart control reg
.equ  UBRR   =$09 ; uart baud reg
.equ  ACSR   =$08 ; analog comparator control and status reg

;***** Bit Definitions

;---  SREG   =$3f ; status register
.equ  _SRGIE =7 ; global interrupt enable
.equ  _SRBCS =6 ; bit copy storage(see BLD, BST instr)
.equ  _SRHCF =5 ; half carry flag
.equ  _SRS   =4 ; sign bit, xor of N & Z
.equ  _SRV   =3 ; Two's complement overflow
.equ  _SRN   =2 ; negative
.equ  _SRZ   =1 ; zero
.equ  _SRC   =0 ; carry

;--- SPL    =$3d ; stack pointer, p13
;  you need to initialize this to the top of RAM, since
;  the stack works down into ram as we push things on the stack,
;  you can use the RAMEND literal as end of ram.
.equ  SP7  =7
.equ  SP6  =6
.equ  SP5  =5
.equ  SP4  =4
.equ  SP3  =3
.equ  SP2  =2
.equ  SP1  =1
.equ  SP0  =0

;--- GIMSK  =$3b ; general interrupt mask reg, p17 
.equ  INT1  =7 ; external interrupt request 1 enable
.equ  INT0  =6 ; external interrupt request 0 enable

;--- GIFR   =$3a ; general interrupt flag reg, p18
.equ  INTF1  =7 ; external inter. flag1, r/w
.equ  INTF0  =6 ; external inter. flag0. r/w

;--- TIMSK  =$39 ; timer Interrupt mask reg, p18
.equ  TOIE1  =7 ; timer1 overflow interrupt enable, r/w
.equ  OCIE1A =6 ; timer1 output compare match, r/w
.equ  TICIE  =3 ; timer1 input capture interrupt enable, r/w
.equ  TOIE0  =1 ; timer0 overflow interrupt enable, r/w

;--- TIFR   =$38 ; timer interrupt flag reg, p18
.equ  TOV1  =7 ; timer1 overflow flag r/w
.equ  OCF1A =6 ; output compare flag 1A
.equ  ICF1  =3 ; input capture flag 1
.equ  TOV0  =1 ; timer0 overflow flag 1

;--- MCUCR  =$35 ; MCU general control reg, p19
.equ  SE    =5 ; Sleep Enable
.equ  SM    =4 ; Sleep Mode
.equ  ISC11 =3 ; Interrupt Sense Control 1 bit 1
.equ  ISC10 =2 ; Interrupt Sense Control 1 bit 0
.equ  ISC01 =1 ; Interrupt Sense Control 0 bit 1
.equ  ISC00 =0 ; Interrupt Sense Control 0 bit 0

.equ  EXTRF =1
.equ  PORF  =0

;--- TCCR0  =$33 ; timer/counter 0 control reg, p22
.equ  CS02  =2 ; clock select bit 2
.equ  CS01  =1 ; clock select bit 1
.equ  CS00  =0 ; clock select bit 0
; where 0=stop, 1=CK, 2=CK/8, 3=CK/64, 4=CK/256, 5=CK/1024,
;   6=ext pin T0-falling 7=ext pin T0-rising

;--- TCNT0  =$32 ; timer/counter 0, 8-bit
 ; byte value of timer

;---  TCCR1A =$2f ; timer/counter 1, control reg A
.equ  COM1A1 =7 ; Compare output mode1, bit 1
.equ  COM1A0 =6 ; Compare output mode1, bit 0
  ; where pin OC1, 0=disconnect, 1-toggle, 2=clear, 3=set
.equ  PWM11  =1 ; pulse width modulation select bit 1
.equ  PWM10  =0 ; pulse width modulation select bit 0
  ; where 0=disable, 1=timer1 8bit, 2=timer1 9bit, 3=timer1 10bit

;---  TCCR1B =$2e ; timer/counter 1, control reg B
.equ  ICNC1  =7 ; input capture noise canceler(4 CKs)
.equ  ICES1  =6 ; input capture edge select 0=falling edge, 1=rising
.equ  CTC1  =3 ; clear timer1 on compare match
.equ  CS12  =2 ; clock select1 bit 2(prescaler source of timer1)
.equ  CS11  =1 ; clock select1 bit 1
.equ  CS10  =0 ; clock select1 bit 0
; where 0=stop, 1=CK, 2=CK/8, 3=CK/64, 4=CK/256, 5=CK/1024,
;   6=ext pin T1-falling 7=ext pin T1-rising

;--- TCNT1H =$2d ; timer/counter 1, high byte, pg25
;--- TCNT1L =$2c ; timer/counter 1, low byte

;--- OCR1AH =$2b ; output compare reg high byte
;--- OCR1AL =$2a ; output compare reg low byte

;--- ICR1H  =$25 ; timer 1 input capture reg high byte
;--- ICR1L  =$24 ; timer 1 input capture reg low byte

;--- WDTCR  =$21 ; watchdog timer control reg, p28
.equ  WDTOE =4 ; watchdog turnoff enable
.equ  WDE   =3 ; watchdog enable
.equ  WDP2  =2 ; watchdog timer prescaler bit 2
.equ  WDP1  =1 ; watchdog timer prescaler bit 1
.equ  WDP0  =0 ; watchdog timer prescaler bit 0
; where WDP# 0=16K, 1=32K, 2=64K, 3=128K, 4=256K, 5=512K, 6=1024K, 7=2048K

;--- EEAR   =$1e ; eeprom address reg
;--- EEDR   =$1d ; eeprom data reg

;--- EECR   =$1c ; eeprom control reg
.equ  EEMWE =2 ; eeprom master write enable
.equ  EEWE  =1 ; eeprom write enable
.equ  EERE  =0 ; eeprom read enable

;--- PORTB  =$18 ; port b(pb7..pb0), pg38
.equ  PB7  =7 ; pin19, SCK, serial clock for SPI
.equ  PB6  =6 ; pin18, MISO, data out for SPI
.equ  PB5  =5 ; pin17, MOSI, data in for SPI
.equ  PB4  =4 ; pin16, 
.equ  PB3  =3 ; pin15, OC1, Timer1 output compare match output
.equ  PB2  =2 ; pin14, 
.equ  PB1  =1 ; pin13, AIN1, analog comparator negative input
.equ  PB0  =0 ; pin12, AIN0, analog comparator positive input

;--- DDRB   =$17 ; data direction reg, port b, pg38
.equ  DDB7  =7
.equ  DDB6  =6
.equ  DDB5  =5
.equ  DDB4  =4
.equ  DDB3  =3
.equ  DDB2  =2
.equ  DDB1  =1
.equ  DDB0  =0
  ; where DDBx=0 PORTBx=0 ---> Tri State
  ;       DDBx=0 PORTBx=1 ---> Will source current if ext. pulled low
  ;       DDBx=1 PORTBx=0 ---> push pull zero output
  ;       DDBx=1 PORTBx=1 ---> push pull one output

;--- PINB   =$16 ; input pins, port b
.equ  PINB7  =7
.equ  PINB6  =6
.equ  PINB5  =5
.equ  PINB4  =4
.equ  PINB3  =3
.equ  PINB2  =2
.equ  PINB1  =1
.equ  PINB0  =0

;--- PORTD  =$12 ; data reg, port d(pd6..pd0), pg43
.equ  PD6  =6 ; pin 11, ICP, timer1 input capture pin
.equ  PD5  =5 ; pin 9, T1, timer1 external input
.equ  PD4  =4 ; pin 8, T0, timer0 external input
.equ  PD3  =3 ; pin 7, INT1, ext. interrupt1 input
.equ  PD2  =2 ; pin 6, INT0, ext. interrupt0 input
.equ  PD1  =1 ; pin 3, TXD, transmit data output to UART
.equ  PD0  =0 ; pin 2, RXD, receive data input to UART

;--- DDRD   =$11 ; data direction reg, port d
.equ  DDD6  =6
.equ  DDD5  =5
.equ  DDD4  =4
.equ  DDD3  =3
.equ  DDD2  =2
.equ  DDD1  =1
.equ  DDD0  =0
  ; where DDDx=0 PORTDx=0 ---> Tri State
  ;       DDDx=0 PORTDx=1 ---> Will source current if ext. pulled low
  ;       DDDx=1 PORTDx=0 ---> push pull zero output
  ;       DDDx=1 PORTDx=1 ---> push pull one output


;--- PIND   =$10 ; input pins, port d
.equ  PIND6  =6
.equ  PIND5  =5
.equ  PIND4  =4
.equ  PIND3  =3
.equ  PIND2  =2
.equ  PIND1  =1
.equ  PIND0  =0

;--- UDR    =$0c ; uart io data reg. pg33

;--- USR    =$0b ; uart status reg
.equ  RXC  =7 ; uart receive complete
.equ  TXC  =6 ; uart transmit complete
.equ  UDRE =5 ; uart tx data holding register empty
.equ  FE   =4 ; framing error
.equ  OR   =3 ; overrun

;--- UCR    =$0a ; uart control reg
.equ  RXCIE =7  ; rx complete interrupt enable
.equ  TXCIE =6  ; tx complete interrupt enable
.equ  UDRIE =5  ; uart data reg empty interrupt enable
.equ  RXEN  =4  ; receiver enable
.equ  TXEN  =3  ; transmitter enable
.equ  CHR9  =2  ; 9bit chars
.equ  RXB8  =1  ; receive data bit 8
.equ  TXB8  =0  ; transmit data bit 8

;--- UBRR   =$09 ; uart baud reg
  ; where baud = clk / (UBRR + 1)

;--- ACSR   =$08 ; analog comparator control and status reg,pg36
.equ  ACD   =7 ; analog comparator disable
.equ  ACO   =5 ; analog comparator output
.equ  ACI   =4 ; analog comparator input flag
.equ  ACIE  =3 ; analog comparator input enable
.equ  ACIC  =2 ; analog comparator capture enable
.equ  ACIS1 =1 ; analog comparator interrupt mode bit 1
.equ  ACIS0 =0 ; analog comparator interrupt mode bit 0
  ; where 0=interrupt on toggle, 1=reserved, 2=interrupt on falling, 3=rising

;--- special indexing registers
.def  XL  =r26
.def  XH  =r27
.def  YL  =r28
.def  YH  =r29
.def  ZL  =r30
.def  ZH  =r31

.equ    RAMEND  =$df    ;Last On-Chip SRAM Location

.equ  INT0addr=$001  ;External Interrupt0 Vector Address
.equ  INT1addr=$002  ;External Interrupt1 Vector Address
.equ  ICP1addr=$003  ;Input Capture1 Interrupt Vector Address
.equ  OC1addr =$004  ;Output Compare1 Interrupt Vector Address
.equ  OVF1addr=$005  ;Overflow1 Interrupt Vector Address
.equ  OVF0addr=$006  ;Overflow0 Interrupt Vector Address
.equ  URXCaddr=$007  ;UART Receive Complete Interrupt Vector Address
.equ  UDREaddr=$008  ;UART Data Register Empty Interrupt Vector Address
.equ  UTXCaddr=$009  ;UART Transmit Complete Interrupt Vector Address
.equ  ACIaddr =$00a  ;Analog Comparator Interrupt Vector Address

;--------------- Instruction Summary
;ARITHMETIC AND LOGIC INSTRUCTIONS
;ADD Rd, Rr Add two Registers Rd