📄 codec_processing_isr.asm
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/* **************************************************************************************************
/ /
/ AD1819A - SPORT1 TX INTERRUPT SERVICE ROUTINE /
/ /
/ Receives MIC1/Line input data from the AD1819A via SPORT1 and transmits processed audio data /
/ back out to the AD1819A Stereo DACs/Line Outputs /
/ /
/ This SPORT1 tx ISR version uses the ADC Valid Bits to send and recieve audio samples at /
/ different rates other than the default 48 kHz. Assuming the L/R ADCs and DACs are running /
/ at the same sample rate, we transmit a processed sample for every newly recieved ADC sample. /
/ /
*****************************************************************************************************
/
This Serial Port 1 Transmit Interrupt Service Routine performs arithmetic computations on /
the SPORT1 receive DMA buffer (rx_buf) and places results to SPORT1 transmit DMA buffer (tx_buf) /
/
rx_buf[5] - DSP SPORT recieve buffer /
Slot # Description DSP Data Memory Address /
------ -------------------------------------- ------------------------------------------------- /
0 AD1819A Tag Phase DM(rx_buf + 0) = DM(rx_buf + TAG_PHASE) /
1 Status Address Port DM(rx_buf + 1) = DM(rx_buf + STATUS_ADDRESS_SLOT) /
2 Status Data Port DM(rx_buf + 2) = DM(rx_buf + STATUS_DATA_SLOT) /
3 Master PCM Capture (Record) Left Chan. DM(rx_buf + 3) = DM(rx_buf + LEFT) /
4 Master PCM Capture Right Channel DM(rx_buf + 4) = DM(rx_buf + RIGHT) /
/
tx_buf[7] - DSP SPORT transmit buffer /
Slot # Description DSP Data Memory Address /
------ -------------------------------------- -------------------------------------------------- /
0 ADSP-21065L Tag Phase DM(tx_buf + 0) = DM(tx_buf + TAG_PHASE) /
1 Command Address Port DM(tx_buf + 1) = DM(rx_buf + COMMAND_ADDRESS_SLOT) /
2 Command Data Port DM(tx_buf + 2) = DM(rx_buf + COMMAND_DATA_SLOT) /
3 Master PCM Playback Left Channel DM(tx_buf + 3) = DM(rx_buf + LEFT) /
4 Master PCM Playback Right Channel DM(tx_buf + 4) = DM(rx_buf + RIGHT) /
5 Dummy Slot (Not Used) /
6 Dummy Slot (Not used) /
/
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~/
/
** IMPORTANT SPORT-AD1819A CODEC TDM TIMING NOTES: /
------------------------------------------------- /
For SPORT TX and RX DMA chaining in TDM mode with equivalent DMA buffer sizes & active TDM /
channels, the DMA interrupts are alway at least two timeslots apart. That is because the tx /
TCB initially places the first two words from the tx DMA buffer into the SPORT1 TX buffer /
registers. This automatically decrements the tx DMA count by two. /
/
For an active 5-channel TX and RX DMA/TDM scheme with SPORT TX ISR processing: after the /
assertion of the TX DMA interrupt, we would need to wait until the RX DMA brings in data for /
channels 4 and 5 for the current frame in which the rx ADC valid bits and DAC request bits are /
set. /
/
So, before timeslot 0 rx and tx, the rx DMA count = 5, while the tx DMA count = 3. The /
transmit interrupt occurs when the tx count = 0. This occurs immediately after timeslot 2. While /
this occurs, the tx data for the left channel is shifting out of this Tx-shift register in /
slot 3, while the right tx data for channel 4 is in the TX1A register queue. /
/
After both the transmit and recieve interrupts are latched in the current frame (after /
timeslot 5), the TCBs will be reloaded, but no DMA internal memory transfers will occur until /
the next frame sync, which would occur 11 time-slots later. After each reloading of the tx /
TCB, the first 2 words of the TX DMA buffer are automatically loaded into the TX queue as the /
previous 2 words at the end of the last TX DMA transfer are shifted out of the SPORT tx shift /
register. /
/
__ __ /
RFS1 ___| |________________________________________________________________________| |_ /
/
DR1_A < SLOT0 >< SLOT1 >< SLOT2 >< SLOT3 >< SLOT5 > ----------//-------------- /
No activity on Slots 5 - 15 /
/
CR1A 5 4 3 2 1 0 <-- RX Interrupt Here /
(DMA RX Count Reg) /
/
/
DT1_A < SLOT0 >< SLOT1 >< SLOT2 >< SLOT3 >< SLOT5 > ----------//---------------- /
No activity on Slots 5 - 15 /
/
CT1A 3 2 1 0 <-- TX Interrupt Here /
(DMA TX Count Reg) TX queue reloaded with 1st two tx_buf values /
/
(1 / 12.288 MHz SCLK) x (16-bits/timeslot) x (2 timeslots) = 2.604 microseconds /
1 / 60 MHz Instruction Execution = 16.667 nanoseconds per instruction /
2.604 microseconds / 16.667 nanoseconds = 156.25 = 157 DSP cycles /
/
/
Keeping these differences in interrupt timing between the transmit and recieve channels, we can /
implement different methods to ensure proper data and tag alignment for processing data at /
sample rates < 48 kHz with a 48 kHz audio frame rate. /
/
1) One workaround is to implement a delay loop (in the tx ISR) to wait for the data if /
we have a SPORT1 TX DMA buffer size of 5 & 5 active TDM channels, equivalent in size to /
the SPORT1 RX DMA buffer and enabled rx channels. Before getting the data a wait loop can /
be added to wait for the data. This can be coded as follows: /
/
LCNTR=126, Do Delay_Getting_Data UNTIL LCE; /
Delay_Getting_Data: NOP; /
/
Thus, if wishing to run at sample rates < 48 kHz with a 48 kHz frame rate, the user /
will need to add the above delay loop when processing data from the TX interrupt /
/
It is estimated that while waiting for the left channel in slot 3, it takes 79 DSP /
cycles. While waiting for the right channel data in slot 4, it takes apprx 157 DSP cycles. /
Because of the interrupt latency and previous instructions to this point, it was found /
that a Loop counter value of 126 guarantees enough time for the right channel /
data to be receieved. /
/
This approach is probably unacceptable for most designs. Since other processing or /
interrupts usually need to be executed during this time and because of the loss in MIPs /
bandwidth (about 12% loss in bandwidth utilization) then the user should try steps 2, 3 /
and 4. The loss in bandwidth waiting for the 4th and 5th slots is estimated as follows: /
/
(60 MIPs / 48 kHz AC-97 Audio Frame Rate) = 1250 DSP cycles to process data /
1250 DSP cycles - 150 = 1100 DSP cycles, or about 12% loss in available MIPs /
/
2) Extend the TX DMA buffer size to 7 in length and enable 7 tx TDM channels, as is done /
in this code example. This guarantees that by the time we generate a TX DMA interrupt, /
the RX left and right data for the current frame have been recieved in time before we /
read the samples. Slots 5 and 6 are dummy slots and never used. However, the DSP core /
is not held up waiting for the current rx left and right channels to be DMA'ed into RX_BUF. /
In order to implement this with the 21065L EZ-LAB RS232 Debugger, the user is required to /
run a SPORT1 register clear routine to reset SPORT1 MCM and DMA activity. /
/
3) Use the SPORT Rx Interrupt for audio processing. Enable only 5 active RX channels (0-4) /
with a 5-word RX DMA buffer. Extend the TX DMA buffer size to 16, and enable 16 TDM /
channels (0 - 15). This method allows you to use the RX interrupt for processing without /
having to install the ISR call in the SPORT vector location. Left/Right TAG & audio data /
is in the new buffer upon interrupt assertion, and we still have plenty of time (approx /
770 DSP cycles) in order to write to the TX TAG slotbefore it is shifted from the DMA /
buffer to the SPORT tx shift register. The only disadvantage of this method is that you /
spend 11 wasted IOP bus cycles for dummy TX slots that are not used. Refer to alternate /
AD1819A reference code for this solution. /
/
4) Otherwise, we can keep the RX and TX DMA buffer sizes and active MCM channels to 5, and /
then use both the SPORT1 tx and rx interrupts to send/receive AD1819a audio data. /
Refer to alternate AD1819A reference code for this solution. /
/
*** Using approach # 2 and #4, we have approximately 75 DSP cycles upon entering the TX /
interrupt service routineto write to the DM(TX_BUF + 0), which is the TX TAG phase slot, in /
order that our left and right transmit data slots go out within the same audio frame as the TAG /
slot. If not done in time, we would send data out in the current frame, but the tag bits would /
get sent in the following frame. We would then risk the dropping of processed samples, and /
severe audible distortion results. The example below ensures that the tx TAG bits are set at /
the beginning of the ISR before any audio processing is done. /
/
Comments regarding approach # 3 and RX-based processing: /
For fixed 48 kHz sample rate applications, the RX interrupt can be used with 5-word rx & tx DMA /
buffers and 5 rx/tx TDM channels active, since the RX and TX TAG bits and valid left/right data /
occur in every frame. One audio frame delay would result in the transmitting of the processed /
data, but in realtime the latency (One 48 kHz frame delay) would be too negligible that it is /
not a concern. If the DMA buffers are not adjusted to account for slower sample rates using /
RX-ISR processing, then when the RX DMA interrupt occurs, the Tx TAG slot data in the top of /
the buffer has already been loaded into the TX1A register waiting for the next frame sync, so /
it would already have been too late to write to the tag slot for the next frame. Extending the /
tx DMA buffer size will delay the shifting of the tag slot to the SPORT queue so you will have /
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